Strained SiGe PFET Channel Integration With Silicon NFETs
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Solution Overview
Problem
As semiconductor devices continue to scale, integrating a silicon channel for n-type field-effect transistors (NFET) and a strained SiGe channel for p-type field-effect transistors (PFET) on the same wafer becomes increasingly challenging, requiring improvements in CMOS device fabrication to maintain carrier charge mobility and reduce process complexity.
Innovation Solution
The implementation of a semiconductor structure with a p-type field-effect transistor region featuring a strained channel composed of silicon germanium and silicon, and an n-type field-effect transistor region with a silicon channel, allowing for improved carrier charge mobility without significantly increasing process complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a strained SiGe channel is used for PFET devices, then carrier charge mobility is improved, but process complexity increases when integrating with NFET silicon channels on the same wafer
Solution Approach 1:
The wafer is divided into distinct PFET regions and NFET regions, with each region containing channels optimized for its specific transistor type. The PFET region contains strained SiGe channels while the NFET region contains silicon channels, allowing each segment to be independently optimized without compromising the other.
Solution Approach 2:
Different channel materials and strain conditions are applied locally to different regions of the wafer. The PFET regions receive strained SiGe channels to enhance hole mobility, while NFET regions use standard silicon channels for electron transport, ensuring each local area has the optimal material properties for its intended function.
2Productivity
If geometry size is decreased to increase device density, then productivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent transitions from planar transistor architectures to vertically-oriented FinFET structures, utilizing the third dimension (vertical height) to increase effective channel area and device density without proportionally reducing lateral geometry dimensions. This dimensional transition allows continued scaling while maintaining manufacturability.
Solution Approach 2:
The use of composite SiGe materials with controlled germanium composition ratios allows optimization of both mechanical properties for strain engineering and electrical properties for carrier mobility, enabling precise control over channel characteristics at scaled dimensions while maintaining manufacturing feasibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances carrier charge mobility in PFET devices compared to unstrained silicon germanium channels, while maintaining the simplicity of integrating both types of channels on the same wafer, addressing the scaling challenges in CMOS device fabrication.
Implementation Method 1
a strained channel comprising a composite of silicon germanium and silicon
Data Source
AI summary
A semiconductor structure includes a p-type field-effect transistor region and an n-type field-effect transistor region. The p-type field-effect transistor region includes a strained channel of a composite of silicon germanium and silicon. The n-type field-effect transistor region includes a silicon channel.