Strained SiGe and SiC Transistors for Mobility
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Solution Overview
Problem
The continuous reduction of transistor dimensions in integrated circuits poses challenges in reliably creating critical circuit elements and achieving enhanced charge carrier mobility, leading to complex process adaptations and potential performance limitations.
Innovation Solution
The use of differently strained semiconductor materials, such as silicon/germanium and silicon/carbon alloys, embedded in drain and source regions of transistors, with sophisticated manufacturing techniques like epitaxial growth and stress memorization, to enhance transistor performance without increasing process complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor dimensions are continuously reduced to increase integration density, then more transistors can be provided on a chip, but the reliability of creating critical circuit elements deteriorates and process complexity increases
Solution Approach 1:
The patent changes the physical state and properties of semiconductor materials by introducing strain through silicon/germanium and silicon/carbon alloys. This strain modifies the lattice structure and charge carrier mobility, enabling performance enhancement without further dimension reduction, thus avoiding the reliability issues associated with continuous scaling
Solution Approach 2:
The patent employs composite semiconductor structures combining silicon with germanium and carbon alloys in drain and source regions. These composite materials provide both the strain necessary for enhanced carrier mobility and the structural integrity needed for reliable fabrication at existing critical dimensions
2Productivity
If transistor dimensions are reduced to increase integration density, then more transistors can be provided on a chip, but charge carrier mobility deteriorates leading to performance limitations
Solution Approach 1:
The patent modifies the physical parameters of the semiconductor channel by introducing mechanical strain through embedded silicon/germanium and silicon/carbon alloys in the drain and source regions. This strain engineering approach directly enhances charge carrier mobility by altering the band structure and reducing scattering, thereby improving transistor speed without requiring further dimension reduction
Solution Approach 2:
The patent applies strain-inducing materials selectively in the drain and source regions adjacent to the channel, creating localized strain fields that enhance carrier mobility precisely where needed for charge injection and extraction, without affecting other parts of the transistor structure
3Speed
If conventional strain induction methods are used to enhance carrier mobility, then transistor performance improves, but process complexity increases
Solution Approach 1:
The patent combines the formation of silicon/germanium and silicon/carbon alloy regions into a unified strain engineering approach that simultaneously benefits both NMOS and PMOS transistors. By using similar material systems and fabrication techniques for both transistor types, the process complexity is reduced compared to treating each transistor type separately
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances charge carrier mobility and transistor performance by providing efficient strain mechanisms, reducing process complexity, and improving manufacturing efficiency, while minimizing additional implantation-induced damage and floating body effects.
Implementation Method 1
creating tensile or compressive stress in the vicinity of the channel region to produce a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively
Implementation Method 2
subsequently the silicon/germanium layer is selectively formed in the PMOS transistor by epitaxial growth
Data Source
AI summary
A silicon/germanium material and a silicon/carbon material may be provided in transistors of different conductivity type on the basis of an appropriate manufacturing regime without unduly contributing to overall process complexity. Furthermore, appropriate implantation species may be provided through exposed surface areas of the cavities prior to forming the corresponding strained semiconductor alloy, thereby additionally contributing to enhanced overall transistor performance. In other embodiments a silicon/carbon material may be formed in a P-channel transistor and an N-channel transistor, while the corresponding tensile strain component may be overcompensated for by means of a stress memorization technique in the P-channel transistor. Thus, the advantageous effects of the carbon species, such as enhancing overall dopant profile of P-channel transistors, may be combined with an efficient strain component while enhanced overall process uniformity may also be accomplished.