Strained SiGe Source-Drain Fabrication for Carrier Mobility

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Solution Overview

Problem

In semiconductor device fabrication, particularly in CMOS technology, it is challenging to achieve enhanced carrier mobility as strained materials struggle to deliver sufficient strain to the channel region, leading to device instability and potential failure, especially as gate length and spacing decrease.

Innovation Solution

A method is developed to fabricate a semiconductor device with a strained structure by forming gate stacks, recess cavities, and source/drain features using selectively grown silicon germanium (SiGe) to induce strain in the channel region, involving multiple epitaxial growth layers and careful etching processes to optimize strain distribution and reduce loading effects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If strained materials are used in source and drain recess cavities to enhance carrier mobility, then device performance is improved, but the strained materials cannot deliver sufficient strain into the channel region, leading to device instability and failure

Engineering Contradiction:
Improvedevice stabilityVSAvoidstrain delivery consistency
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies local quality by creating different strain conditions in different regions of the device. Specifically, it forms relaxed SiGe regions adjacent to the channel that provide strain, while the channel region itself maintains the strain benefit. This localized approach ensures that strain is delivered precisely where needed without compromising device stability.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent implements nesting by forming multiple layers and regions within the source and drain structures. It creates a nested configuration where strained SiGe is surrounded by relaxed SiGe, which is in turn surrounded by other structural elements. This nested arrangement allows strain to be contained and delivered effectively to the channel region while maintaining overall device integrity.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Productivity

If gate length and spacing between devices are decreased to scale down the semiconductor device, then device integration is improved, but strained materials struggle to deliver sufficient strain into the channel region

Engineering Contradiction:
Improvedevice integration densityVSAvoidcarrier mobility enhancement
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies parameter changes by carefully controlling the composition, thickness, and crystal structure of the SiGe layers. It adjusts the germanium content and layer dimensions to optimize strain delivery in scaled-down devices. By modifying these parameters, the patent ensures that sufficient strain is delivered to the channel region even as gate length and device spacing are reduced for higher integration density.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method effectively increases the volume of strained material adjacent to isolation structures, enhancing carrier mobility and improving device performance by ensuring a consistent strain delivery to the channel region, thereby stabilizing and upgrading semiconductor device performance.

Implementation Method 1

strained structures in source and drain (S/D) recess cavities of the MOSFET utilizing selectively grown silicon germanium (SiGe) may be used to enhance carrier mobility

Methodology Applied
Scientific EffectStrain: Deformation

Implementation Method 2

forming a first epitaxial (epi) material in the recess cavity, forming a second epi material over the first epi material

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS10134897B2Semiconductor device and fabrication method thereof
Publication Date: 2018.11.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10134897B2 patent drawing
  • US10134897B2 patent drawing
  • US10134897B2 patent drawing

AI summary

A semiconductor device and a method for fabricating the semiconductor device are disclosed. A gate stack is formed over a surface of the substrate. A recess cavity is formed in the substrate adjacent to the gate stack. A first epitaxial (epi) material is then formed in the recess cavity. A second epi material is formed over the first epi material. A portion of the second epi material is removed by a removing process. The disclosed method provides an improved method by providing a second epi material and the removing process for forming the strained feature, therefor, to enhance carrier mobility and upgrade the device performance.