Strained SiGe Transistor with Hexagonal Cavity Offset Reduction
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Solution Overview
Problem
The challenge in integrated circuit fabrication is to enhance charge carrier mobility in transistor channel regions while maintaining the integrity of the gate electrode structure, as reducing the channel length and lateral offset of silicon/germanium alloy can lead to mobility degradation and defects.
Innovation Solution
The approach involves forming cavities adjacent to the gate electrode structure with a protection layer to maintain their shape during high-temperature processes, allowing for a reduced lateral offset and increased strain in the channel region, using a combination of plasma and wet etch processes to create non-rectangular cavities and depositing a strain-inducing semiconductor alloy at a lower temperature to prevent silicon reflow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If high-temperature processes are used to form silicon/germanium alloy, then alloy deposition is enhanced, but silicon reflow occurs causing cavity shape distortion
Solution Approach 1:
The protection layer is deposited in advance before the alloy formation process. This layer prevents silicon reflow during high-temperature processing, maintaining the cavity's geometric shape while still allowing effective alloy deposition.
Solution Approach 2:
The protection layer acts as an intermediary between the silicon cavity and the high-temperature processing environment. It mediates the thermal stress and prevents direct silicon reflow, allowing the cavity shape to be maintained during alloy deposition.
2Speed
If the channel length is reduced to increase operating speed, then circuit performance is improved, but charge carrier mobility degrades
Solution Approach 1:
The lateral offset parameter of the silicon/germanium alloy is changed to be smaller than conventional values. This parameter change enhances the strain effect in the channel region, improving charge carrier mobility even when the channel length is reduced for higher operating speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the strain component in the channel region, improving transistor performance without compromising the gate electrode integrity, enabling more flexible cavity design and increased production yield.
Implementation Method 1
forming cavities in a silicon-containing crystalline semiconductor region adjacent to a gate electrode structure of a transistor of a semiconductor device. The method further comprises forming a protection layer on exposed surfaces of the cavities and introducing the semiconductor device into a process ambient at an elevated first temperature
Implementation Method 2
a combination of plasma and wet etch processes to create non-rectangular cavities
Implementation Method 3
a combination of plasma and wet etch processes to create non-rectangular cavities
Implementation Method 4
depositing a strain-inducing semiconductor alloy at a lower temperature to prevent silicon reflow. This method enhances the strain component in the channel region, improving transistor performance
Data Source
AI summary
A strain-inducing semiconductor alloy may be formed on the basis of cavities which may have a non-rectangular shape, which may be maintained even during corresponding high temperature treatments by providing an appropriate protection layer, such as a silicon dioxide material. Consequently, a lateral offset of the strain-inducing semiconductor material may be reduced, while nevertheless providing a sufficient thickness of corresponding offset spacers during the cavity etch process, thereby preserving gate electrode integrity. For instance, P-channel transistors may have a silicon/germanium alloy with a hexagonal shape, thereby significantly enhancing the overall strain transfer efficiency.