Strained Silicon-on-Insulator Structures via Buried Oxide Thickness Variation
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Solution Overview
Problem
Existing silicon-on-insulator (SOI) structures face challenges in introducing tensile strain into the active layer without using underlying silicon germanium layers, which can introduce defects, affect thermal conductivity, and complicate device optimization for n-channel and p-channel field effect transistors.
Innovation Solution
The method involves thickening specific regions of the buried insulating layer to transfer tensile stress to the active layer, thereby straining it locally without adding additional layers, enhancing carrier mobility without the drawbacks of silicon germanium layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon germanium layers are introduced to induce tensile strain in the active layer, then carrier mobility is improved, but device yields deteriorate due to introduced defects
Solution Approach 1:
The patent removes the silicon germanium layer from the device structure entirely, extracting the harmful element while preserving the beneficial tensile strain effect. The method achieves strain induction through alternative means (buried oxide layer thickness variation) without requiring the problematic silicon germanium intermediate layer, thereby eliminating defect introduction while maintaining carrier mobility enhancement.
Solution Approach 2:
The patent uses the buried oxide layer as an intermediary mechanism to transfer tensile strain to the active layer. By varying the thickness of the buried oxide layer, strain is indirectly imposed on the active layer without direct contact with silicon germanium, achieving the same mobility enhancement effect through a different physical pathway that avoids defect generation.
2Stress or pressure
If silicon germanium layers are used for strain introduction, then tensile strain is achieved, but thermal conductivity deteriorates
Solution Approach 1:
The patent extracts the silicon germanium layer from the structure, removing the thermal conductivity bottleneck. By achieving strain induction through buried oxide layer thickness control rather than silicon germanium integration, the method eliminates the thermal management problems associated with low-conductivity silicon germanium layers while maintaining the required tensile strain in the active layer.
3Stability of the object's composition
If silicon germanium layers are deposited across the wafer, then uniform tensile strain is achieved, but device optimization for separate n-channel and p-channel transistors becomes difficult
Solution Approach 1:
The patent applies local quality by varying the buried oxide layer thickness in different spatial regions of the wafer to achieve different strain levels. This allows NFETs and PFETs to be optimized independently with appropriate strain levels tailored to each transistor type, while still using a single continuous buried oxide layer structure rather than separate silicon germanium layers for each device type.
4Reliability
If silicon germanium layers are used to increase strain, then carrier mobility is enhanced, but the active layer thickness increases
Solution Approach 1:
The patent removes the silicon germanium layer that would otherwise add to the overall structure thickness. By achieving strain induction through controlled variation in buried oxide layer thickness rather than adding silicon germanium layers, the method enhances carrier mobility while maintaining the active layer at the required thin dimensions for modern device scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves carrier mobility by up to twenty percent, enhancing device performance without the limitations of silicon germanium layers, such as defects and thermal conductivity issues, and allows for optimized strain introduction for both n-channel and p-channel transistors.
Implementation Method 1
The insulating layer has a thickened region transferring tensile stress to the active layer effective to induce strain in a strained region of the active layer
Data Source
AI summary
A silicon-on-insulator (SOI) device and structure having locally strained regions in the silicon active layer formed by increasing the thickness of underlying regions of a buried insulating layer separating the silicon active layer from the substrate. The stress transferred from the underlying thickened regions of the insulating layer to the overlying strained regions increases carrier mobility in these confined regions of the active layer. Devices formed in and on the silicon active layer may benefit from the increased carrier mobility in the spaced-apart strained regions.