Strained Silicon CMOS Device With Silicon Germanium Source Drain
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional integrated circuit manufacturing processes face challenges in reducing device size and improving switching speed while maintaining signal clarity, due to limitations in process technology and material constraints, particularly in the production of MOS devices.
Innovation Solution
The use of strained silicon structures, specifically forming silicon germanium and silicon carbide materials in source and drain regions to create compressive and tensile strain modes in channel regions of CMOS devices, enhancing mobility and compatibility with existing process technologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device geometry is reduced to increase circuit density, then more devices can be fabricated per wafer, but process limitations prevent further scaling
Solution Approach 1:
The patent introduces strained silicon technology that changes the physical parameters of the semiconductor material by inducing mechanical strain through silicon germanium source/drain structures. This parameter change enables continued device scaling by modifying carrier mobility characteristics, allowing smaller geometries to maintain performance requirements that would otherwise limit further scaling.
Solution Approach 2:
The patent employs composite material structures combining silicon channel regions with silicon germanium source and drain regions. This composite approach allows the silicon channel to maintain its excellent electrical properties while the silicon germanium portions provide the necessary strain induction and compatibility with existing CMOS fabrication processes, thereby enabling further device miniaturization.
2Speed
If device size is reduced to improve switching speed, then faster performance is achieved, but signal clarity deteriorates due to noise
Solution Approach 1:
The strained silicon structure changes the fundamental electrical parameters of the channel by inducing strain that increases carrier mobility. This parameter modification enables smaller devices to achieve higher switching speeds while maintaining sufficient signal integrity, as the enhanced mobility compensates for the reduced device dimensions that would otherwise increase noise susceptibility.
3Productivity
If conventional MOS devices are made smaller, then circuit density increases, but manufacturing complexity increases
Solution Approach 1:
The silicon germanium source/drain structure serves multiple functions simultaneously: it induces strain in the silicon channel to enhance mobility, it is compatible with existing CMOS fabrication processes, and it provides a unified approach that works for both NMOS and PMOS devices. This multi-functionality reduces manufacturing complexity by eliminating the need for separate processing streams for different device types.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases device yields, integrates well with conventional design rules, and improves hole mobility, making it easier to fabricate smaller, faster CMOS devices without requiring substantial modifications to existing equipment or processes.
Implementation Method 1
depositing silicon germanium material into the source region and the drain region to fill the etched source region and the etched drain region. Preferably, the method causes a channel region between the source region and the drain region to be strained in compressive mode from at least the silicon germanium material formed in the source region and the drain region
Data Source
AI summary
A method for forming a CMOS integrated circuit device, the method including; providing a semiconductor substrate, forming a gate layer overlying the semiconductor substrate, patterning the gate layer to form NMOS and PMOS gate structures including edges; forming a first dielectric layer overlying the NMOS and PMOS gate structures to protect the NMOS and PMOS gate structures including the edges, forming a first masking layer overlying a first region adjacent the NMOS gate structure; etching a first source region and a first drain region adjacent to the PMOS gate structure using the first masking layer as a protective layer for the first region adjacent the NMOS gate structure, and depositing a silicon germanium material into the first source and drain regions to cause the channel region between the first source and drain regions of the PMOS gate structure to be strained in a compressive mode.