Strained Silicon CMOS Integration via Single Mask Scheme
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Solution Overview
Problem
Conventional integrated circuit manufacturing processes face challenges in reducing device size and improving switching speeds due to limitations in materials and complex manufacturing processes, particularly in integrating PMOS and NMOS devices for advanced CMOS technologies.
Innovation Solution
The method involves using strained silicon structures by forming a semiconductor substrate with well regions, depositing a polysilicon gate layer, and patterning it with a hard mask to create gate structures, followed by forming liner and spacer dielectric layers, and depositing silicon germanium fill material to strain the channel region, all while using a single additional mask for both PMOS and NMOS devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional manufacturing processes are used to reduce device size, then device geometry becomes smaller, but process limitations prevent further scaling below certain feature sizes
Solution Approach 1:
The patent introduces strained silicon structures that modify the physical and electrical parameters of the semiconductor material. By applying strain to the silicon lattice through specialized growth techniques and material composition adjustments, the invention enables continued device scaling below conventional process limits while maintaining manufacturability through controlled material property changes.
Solution Approach 2:
The invention employs composite material structures combining strained silicon with other materials to achieve both miniaturization and manufacturing feasibility. The strained silicon is integrated within conventional CMOS process frameworks, creating a composite structure that overcomes the limitations of single-material approaches at sub-90nm dimensions.
2Productivity
If device size is reduced to increase circuit density, then more devices fit on each wafer, but manufacturing complexity increases
Solution Approach 1:
The patent segments the manufacturing approach by introducing distinct strained silicon regions for PMOS and NMOS devices through selective epitaxial growth. This segmentation allows independent optimization of each transistor type while maintaining overall process integration, thereby increasing circuit density without proportionally increasing manufacturing complexity.
Solution Approach 2:
The invention performs preliminary strain introduction during the epitaxial growth stage, before subsequent processing steps. By pre-straining the silicon channels early in the fabrication sequence, the patent simplifies later manufacturing steps and reduces overall process complexity while achieving high device density.
3Reliability
If single crystal silicon is used for substrate, then device performance is maintained, but integration of PMOS and NMOS devices becomes complex
Solution Approach 1:
The patent applies local quality changes by introducing strain specifically in the channel regions of PMOS and NMOS devices through selective epitaxial growth. The strained silicon is locally implemented where needed for performance enhancement while maintaining conventional single crystal silicon substrates, thereby improving device integration without compromising overall substrate reliability.
Solution Approach 2:
The strained silicon epitaxial layers serve as intermediary structures between the conventional single crystal silicon substrate and the final PMOS/NMOS device structures. These intermediate strained layers enable sophisticated device integration while preserving the benefits of single crystal substrates, acting as a mediating layer that simplifies the overall integration process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device mobility and yields, is compatible with conventional processes, and supports design rules of 90 nanometers and below, providing improved manufacturing efficiency and integration for CMOS devices.
Implementation Method 1
depositing silicon germanium fill material into the first source region and the first drain region... while causing the first channel region between the first source region and the first drain region to be strained
Data Source
AI summary
A method for forming a CMOS integrated circuit using strained silicon technology. The method forms a liner layer overlying the first gate structure and the second gate structure and overlying first source/drain regions in the first well region and second source/drain regions in the second well region. In a preferred embodiment, the method patterns A spacer dielectric layer to form first sidewall spacer structures on the first gate structure, including the first edges and to form the second sidewall spacer structures on the second gate structure, including the second edges, while using a portion of the liner layer as a stop layer. The method maintains the liner layer overlying the first source/drain regions and second source/drain regions during at least the patterning of the spacer dielectric layer according to a preferred embodiment. The method also etches a first source region and a first drain region adjacent to the first gate structure using the hard mask layer and the first sidewall spacers as a protective layer. The method deposits a silicon germanium fill material into the first source region and the first drain region to fill the etched first source region and the etched first drain region while causing the first channel region between the first source region and the first drain region to be strained in compressive mode from at least the silicon germanium material formed in the first source region and the first drain region.