Strained-Silicon CMOS Transistor Fabrication via Spacer Extraction
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Solution Overview
Problem
The performance of CMOS transistors is limited due to the degradation of silicon germanium's effect on the channel region caused by the position of the spacer in conventional strained-silicon CMOS transistor fabrication methods, which restricts carrier mobility and speed performance.
Innovation Solution
A method involving the removal of the spacer from the gate structure, followed by the deposition of a stress layer on the NMOS transistor and an epitaxial layer in the recess of the PMOS transistor, allowing these layers to be formed closer to the channel region, thereby enhancing electron and hole mobility by applying increased stress and strain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a spacer is formed on the gate sidewall before depositing the epitaxial layer, then the source/drain region can be properly defined and formed, but the epitaxial layer is positioned too far from the channel region, degrading the strain effect on carrier mobility
Solution Approach 1:
The patent removes the spacer structure that was previously necessary for defining source/drain regions. By extracting this intermediate component, the epitaxial layer can be deposited directly adjacent to the gate, eliminating the spacing gap and positioning the strain-inducing layer closer to the channel region for enhanced carrier mobility.
Solution Approach 2:
The source/drain regions are formed prior to epitaxial layer deposition, allowing the epitaxial layer to be positioned immediately adjacent to the gate without requiring a spacer for alignment. This preliminary formation of source/drain regions enables direct contact positioning of the strained silicon layer.
2Ease of manufacture
If the epitaxial layer is deposited with the spacer in place, then the fabrication process follows conventional steps, but the carrier mobility enhancement is limited due to reduced strain effect on the channel region
Solution Approach 1:
The spacer is completely removed from the fabrication process. This extraction eliminates the limitation it imposed on epitaxial layer positioning, allowing the strained silicon layer to extend directly to the gate edge and maximize the strain effect on the channel region, thereby improving transistor performance.
Solution Approach 2:
Instead of using the spacer as a positioning reference for epitaxial layer deposition, the patent inverts the approach by forming source/drain regions first and then depositing the epitaxial layer to directly contact the gate, reversing the conventional sequence to achieve better performance.
3Reliability
If the spacer is removed and epitaxial layer is deposited closer to the gate, then carrier mobility increases due to enhanced strain effect, but the source/drain region definition becomes more challenging
Solution Approach 1:
Source/drain regions are formed in advance before epitaxial layer deposition. This preliminary action establishes precise boundaries for where the epitaxial layer should be deposited, ensuring accurate positioning adjacent to the gate without requiring a spacer for alignment during the epitaxial growth step.
Solution Approach 2:
The source/drain regions serve as an intermediary structure that defines the boundary between the gate and the epitaxial layer. By using the previously formed source/drain regions as a reference, the epitaxial layer can be accurately positioned without needing a spacer, maintaining manufacturing precision while achieving better carrier mobility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases the carrier mobility of both NMOS and PMOS transistors by positioning the stress and epitaxial layers closer to the channel region, improving the overall performance of the CMOS transistors.
Implementation Method 1
a biaxial tensile strain occurs in the epitaxy silicon layer due to the silicon germanium which has a larger lattice constant than silicon, and, as a result, the band structure alters, and the carrier mobility increases
Implementation Method 2
A rapid thermal annealing process is performed thereafter to use a temperature between 900° C. to 1050° C. to activate the dopants within the source/drain region 116 and 117 and repair the lattice structure
Implementation Method 3
A rapid thermal annealing process is performed thereafter to use a temperature between 900° C. to 1050° C. to activate the dopants within the source/drain region 116 and 117 and repair the lattice structure
Implementation Method 4
a selective epitaxial growth process is conducted to form an epitaxial layer 122 in the recess 120 of the NMOS region 102 and the PMOS region 104
Data Source
AI summary
A semiconductor substrate having a first active region and a second active region for fabricating a first transistor and a second transistor is provided. A first gate structure and a second gate structure are formed on the first active region and the second active region and a first spacer is formed surrounding the first gate structure and the second gate structure. A source/drain region for the first transistor and the second transistor is formed. The first spacer is removed from the first gate structure and the second gate structure and a cap layer is disposed on the first transistor and the second transistor and the cap layer covering the second transistor is removed thereafter. An etching process is performed to form a recess in the substrate surrounding the second gate structure. An epitaxial layer is formed in the recess and the cap layer is removed from the first transistor.