Strained-Silicon CMOS Transistor Two-Step Etching Process
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Solution Overview
Problem
Conventional methods for fabricating strained-silicon CMOS transistors face challenges in controlling the etching process, leading to over-etching of the salicide layer and overlapping stress layers, which result in device defects and reduced yield due to the use of a single-step etching method.
Innovation Solution
A two-step etching process is employed, where a first etching stop layer and a stress layer are formed on each transistor region, with a patterned photoresist used to remove the second etching stop layer and a portion of the stress layer in a controlled manner, followed by using the second etching stop layer as a mask to remove the remaining stress layer, thereby preventing over-etching and creating a gap between stress layers to avoid peeling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single-step etching method is used to remove the stress layer, then the fabrication process is simple and fast, but it causes over-etching of the salicide layer and overlapping stress layers leading to device defects
Solution Approach 1:
The single-step etching process is divided into two distinct steps: a first etching step that removes a portion of the stress layer, and a second etching step that removes the remaining stress layer. This segmentation allows for better control of etching magnitude at each stage, preventing over-etching of the salicide layer while ensuring complete removal of the stress layer where needed.
Solution Approach 2:
A gap region is created between adjacent transistor regions before the etching process by selectively removing material in the intermediate area. This preliminary action establishes clear boundaries that prevent stress layer overlap during subsequent etching steps, eliminating the peeling issue that would occur with direct adjacent stress layers.
2Productivity
If stress layers are formed adjacent to each other without a gap, then the device density is high, but the stress layers peel apart causing device defects
Solution Approach 1:
A gap region is preliminarily formed between adjacent transistor regions by selective material removal in the intermediate area before stress layers are fully formed. This preliminary gap prevents direct contact between adjacent stress layers, eliminating the peeling problem while maintaining high device density through optimized spacing.
Solution Approach 2:
The gap region acts as an intermediary space between adjacent stress layers, preventing direct interaction that would cause peeling. This intermediary region allows each stress layer to maintain its structural integrity while still achieving high device density through compact layout design.
3Ease of manufacture
If the etching process is not precisely controlled, then the fabrication process is simple, but the salicide layer is over-etched reducing device yield
Solution Approach 1:
The etching process is segmented into two controlled steps with distinct objectives: the first step removes a controlled portion of the stress layer, and the second step completes the removal. This segmentation provides multiple opportunities to control etching magnitude, preventing salicide layer over-etching while maintaining manufacturing simplicity through standardized process modules.
Solution Approach 2:
The gap region serves as an intermediary structure that physically separates adjacent transistor regions during etching. This intermediary prevents lateral etching from affecting adjacent salicide layers, providing inherent protection against over-etching without requiring complex process control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The two-step etching process effectively controls the etching magnitude, preventing salicide layer over-etching and peeling issues, enhancing the fabrication yield and device integrity by maintaining a precise definition between stress layers.
Implementation Method 1
performing a first etching process to remove the second etching stop layer and a portion of the stress layer of the second active region
Data Source
AI summary
First, a semiconductor substrate having a first active region and a second active region is provided. The first active region includes a first transistor and the second active region includes a second transistor. A first etching stop layer, a stress layer, and a second etching stop layer are disposed on the first transistor, the second transistor and the isolation structure. A first etching process is performed by using a patterned photoresist disposed on the first active region as a mask to remove the second etching stop layer and a portion of the stress layer from the second active region. The patterned photoresist is removed, and a second etching process is performed by using the second etching stop layer of the first active region as a mask to remove the remaining stress layer and a portion of the first etching stop layer from the second active region.