Strained Silicon Transistor Gate Structure Using Silicon Germanium
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Solution Overview
Problem
Conventional methods for manufacturing MOS devices face limitations in reducing device size and improving switching speeds, leading to challenges in increasing circuit density and complexity while maintaining signal clarity, which are difficult to overcome with existing processes and materials.
Innovation Solution
The method involves forming strained silicon structures by depositing silicon germanium or silicon carbide materials into recessed regions of MOS devices, creating a compressive or tensile strain in the channel region between the source and drain regions, using a combination of dielectric layers and etching techniques to pattern gate structures and form sidewall spacers, allowing for improved device performance without significant modifications to conventional equipment or processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device size is reduced to increase circuit density, then more devices can be fabricated on each wafer, but signal clarity becomes difficult to maintain
Solution Approach 1:
The patent applies local quality by introducing strain specifically in the channel region through silicon germanium source and drain extensions, while keeping other regions unchanged. This localized strain enhancement improves carrier mobility and signal clarity in the critical channel area without affecting other device regions, thereby maintaining signal quality even as device dimensions are reduced for higher circuit density.
2Productivity
If device size is reduced to increase circuit density, then more devices can be fabricated on each wafer, but manufacturing complexity increases
Solution Approach 1:
The patent segments the source and drain regions into distinct portions: lightly doped extension regions and heavily doped main regions. This segmentation allows each region to be optimized independently for its specific function while being formed through a integrated process sequence that includes selective epitaxial growth and doping, thereby managing manufacturing complexity through systematic region differentiation.
Solution Approach 2:
The patent employs preliminary action by forming the lightly doped source and drain extensions before the main heavily doped source and drain regions. This preliminary formation of extension regions with specific doping concentrations and profiles prepares the structure for subsequent processing steps, enabling better control over final device characteristics while streamlining the overall manufacturing process.
3Ease of manufacture
If conventional processes are used to reduce device size, then manufacturing is simpler, but switching speeds and performance improvement is limited
Solution Approach 1:
The patent applies parameter changes by modifying the doping concentration profile across different source and drain regions. The lightly doped extensions have lower doping concentrations compared to the heavily doped main regions, creating an optimized gradient that enhances carrier transport and switching speeds. This parameter optimization is achieved through controlled epitaxial growth and selective doping processes that maintain manufacturing feasibility while improving device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device yields, maintains compatibility with existing technology, and increases hole mobility, particularly for CMOS devices, enabling design rules of 65 nanometers and less, while providing a more efficient and integrated process for fabricating advanced integrated circuit devices.
Implementation Method 1
causes a channel region between the source region and the drain region to be strained in compressive mode from at least the silicon germanium material formed in the source region and the drain region
Implementation Method 2
causes a channel region between the source region and the drain region to be strained in tensile mode from at least the silicon germanium material formed in the source region, the drain region, and the gate region
Data Source
AI summary
An integrated circuit semiconductor device, e.g., MOS, CMOS. The device has a semiconductor substrate. The device also has a dielectric layer overlying the semiconductor substrate and a gate structure overlying the dielectric layer. A dielectric layer forms sidewall spacers on edges of the gate structure. A recessed region is within a portion of the gate structure within the sidewall spacer structures. An epitaxial fill material is within the recessed region. The device has a source recessed region and a drain recessed region within the semiconductor substrate and coupled to the gate structure. The device has an epitaxial fill material within the source recessed region and within the drain recessed region. A channel region is between the source region and the drain region is in a strain characteristic from at least the fill material formed in the source region and the drain region. Depending upon the embodiment, the fill material can be any suitable species such as silicon germanium, silicon carbide, and others.