Strained Silicon Germanium Drain Source Protection Layer

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Solution Overview

Problem

The use of high germanium concentrations in silicon/germanium materials for PMOS transistors leads to significant material loss and reduced performance due to degraded stress transfer and dopant loss during manufacturing, resulting in less than expected performance gains in advanced applications.

Innovation Solution

A protection layer is formed on the strained silicon/germanium material before critical process steps to prevent material loss and dopant degradation, ensuring effective stress transfer and maintaining the height level of the silicon/germanium material close to the channel region, thereby enhancing the performance of PMOS transistors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high germanium concentrations are used in silicon/germanium materials for PMOS transistors, then charge carrier mobility in the channel region is enhanced, but material loss and dopant loss occur during manufacturing, reducing performance

Engineering Contradiction:

Improvetransistor performanceVSAvoidsilicon/germanium material loss

Core Design Contradiction:

ReliabilityVSLoss of substance

Solution Approach 1:

A protection layer is formed on the silicon/germanium material before critical manufacturing process steps to prevent material loss and dopant degradation during subsequent processing, thereby preserving the performance-enhancing strain while avoiding manufacturing-related degradation

Inventive Principle:

Principle #10Preliminary action

2Reliability

If high germanium concentrations are used in silicon/germanium materials for PMOS transistors, then charge carrier mobility in the channel region is enhanced, but dopant loss occurs during manufacturing, reducing performance

Engineering Contradiction:

Improvetransistor performanceVSAvoiddopant concentration

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

The protection layer is applied before manufacturing steps that cause dopant loss, preventing degradation of the dopant concentration and maintaining the intended electrical characteristics of the silicon/germanium material throughout the fabrication process

Inventive Principle:

Principle #10Preliminary action

3Speed

If the channel length is reduced to increase operating speed, then the operating speed of integrated circuits is improved, but short channel effects increase, making controllability increasingly difficult

Engineering Contradiction:

Improveoperating speedVSAvoidchannel region controllability

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

Instead of further reducing channel length, the patent changes the parameter of charge carrier mobility by introducing strain through silicon/germanium materials, achieving performance improvement without the negative controllability effects of shorter channels

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The protection layer significantly reduces material loss and dopant loss, maintaining the performance-enhancing strain in PMOS transistors, allowing for improved conductivity and reduced variability in transistor performance.

Implementation Method 1

creating tensile or compressive stress to produce a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively

Methodology Applied

Scientific EffectStrain: Deformation

Implementation Method 2

modification of the lattice structure in the channel region, for instance by creating tensile or compressive stress to produce a corresponding strain

Methodology Applied

Scientific EffectLattice structure modification:

Implementation Method 3

A protection layer is formed on the strained silicon/germanium material before critical process steps to prevent material loss and dopant degradation

Methodology Applied

Scientific EffectPhysical protection:

Implementation Method 4

the compressively strained drain and source regions create uniaxial strain in the adjacent silicon channel region

Methodology Applied

Scientific EffectStress transfer:

Implementation Method 5

enhance charge carrier mobility in the channel region of a PMOS transistor

Methodology Applied

Scientific EffectCharge carrier mobility enhancement:

Data Source

PatentUS8652913B2Method for forming silicon/germanium containing drain/source regions in transistors with reduced silicon/germanium loss

Publication Date: 2014.02.18 GLOBALFOUNDRIES US INC

AI summary

By providing a protection layer on a silicon/germanium material of high germanium concentration, a corresponding loss of strained semiconductor material may be significantly reduced or even completely avoided. The protection layer may be formed prior to critical cleaning processes and may be maintained until the formation of metal silicide regions. Hence, high performance gain of P-type transistors may be accomplished without requiring massive overfill during the selective epitaxial growth process.