Strained-Silicon CMOS via Ion-Implanted Heavy Atoms
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Solution Overview
Problem
The existing methods for forming strained-silicon layers in CMOS devices are costly and complex, requiring multiple epitaxial growth processes, which increase fabrication time and susceptibility to defects, and limit subsequent processing temperatures, thereby degrading performance and increasing costs.
Innovation Solution
The formation of strained-Si layers by amorphous Si deposition or Si epitaxial growth on an ion-implanted Si(x)Heavy-Atom(y) layer, which reduces the need for expensive epitaxial growth processes and allows for a single reactor chamber, thereby decreasing fabrication costs and time, while maintaining enhanced carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple epitaxial growth processes are used to form strained-Si layers, then carrier mobility is enhanced, but fabrication complexity and cost increase
Solution Approach 1:
The patent changes the material composition parameter by incorporating heavy atoms (Ge, Sb, Bi) into the silicon lattice at controlled concentrations (0.1-10 at%). This compositional modification alters the lattice constant, creating strain that enhances carrier mobility without requiring multiple epitaxial growth processes. The heavy atom concentration is precisely controlled to achieve the desired strain effect while maintaining process simplicity.
Solution Approach 2:
The patent extracts the essential function of strain induction from the complex multi-step epitaxial growth process. By removing the need for thick SiGe buffer layers and multiple growth stages, the invention achieves strain induction through a simplified single-step ion implantation process followed by annealing, thereby reducing fabrication complexity while maintaining the carrier mobility enhancement effect.
2Manufacturing precision
If multiple epitaxial growth processes are used, then strained-Si quality is improved, but fabrication time increases
Solution Approach 1:
The patent performs preliminary ion implantation of heavy atoms into the silicon substrate before the final Si layer deposition. This preliminary action creates the strained lattice structure in advance, allowing the subsequent Si layer to inherit the strain without requiring time-consuming multiple epitaxial growth steps. The annealing process then activates the strain effect, achieving high-quality strained-Si in a single fabrication sequence.
3Reliability
If thick SiGe films are used to induce strain, then carrier mobility is enhanced, but processing temperature flexibility is reduced
Solution Approach 1:
The patent changes the strain induction mechanism from relying on thick SiGe films (which constrain temperature processing) to using ion-implanted heavy atoms at controlled concentrations. This parameter change allows the strained-Si layer to be formed without temperature-sensitive thick buffer layers, thereby restoring flexibility in subsequent high-temperature processing steps while maintaining carrier mobility enhancement.
4Reliability
If ion implantation with heavy atoms is used, then strained-Si is formed with enhanced mobility, but fabrication cost may increase
Solution Approach 1:
The patent uses ion implantation of heavy atoms as a disposable, one-time modification step that creates permanent lattice strain. Unlike continuous processes requiring expensive equipment and materials, this method uses a single ion implantation step followed by standard annealing, reducing the need for expensive continuous epitaxial growth equipment and operations, thereby lowering overall fabrication costs despite the initial ion implantation expense.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the complexity and cost of forming strained-Si layers, enhances carrier mobility in CMOS devices, and allows for flexible processing conditions, improving the performance and reliability of integrated circuits without the need for thick SiGe films, thus enabling efficient production of high-performance CMOS devices with sub-0.1 micron technology.
Implementation Method 1
The formation of strained-Si layers by amorphous Si deposition or Si epitaxial growth on an ion-implanted Si(x)Heavy-Atom(y) layer
Implementation Method 2
Si epitaxial growth on an ion-implanted Si(x)Heavy-Atom(y) layer
Implementation Method 3
amorphous Si deposition on a layer of material comprising Si and a 'heavy' atom
Data Source
AI summary
An integrated circuit (IC) includes a strained-silicon layer formed by deposition of amorphous silicon onto either a region of a semiconductor layer that has been implanted with ions to create a larger spacing between atoms in a crystalline lattice of the semiconductor layer or a silicon-ion layer that has been epitaxially grown on the semiconductor layer to have an increased spacing between atoms in the silicon-ion layer. Alternatively, the IC includes a strained-silicon layer formed by silicon epitaxial growth onto the region of the semiconductor layer that has been implanted with ions. The IC also preferably includes a CMOS device that preferably, but not necessarily, incorporates sub-0.1 micron technology. The implanted ions may preferably be heavy ions, such as germanium ions, antimony ions or others. Ion implantation may be done with a single implantation process, as well as with multiple implantation processes.