Strained Silicon MOS Gate Doping via Polysilicon Hard Mask
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Solution Overview
Problem
Conventional methods for manufacturing MOS devices face challenges such as erosion of poly gate spacers and shallow trench isolation during dielectric hard mask removal, and ion-implantation can introduce impurities into PMOS devices, limiting device performance and complexity.
Innovation Solution
A method involving the use of strained silicon structures for CMOS integrated circuits, where a dielectric layer and a hard mask are patterned to form a gate structure with a remaining hard mask portion, allowing for self-aligned polysilicon hard mask removal and dopant implantation without damaging source and drain regions, using a blanket layer for protection and plasma etching to expose the polysilicon gate for doping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional dielectric hard mask removal is used during polysilicon gate patterning, then gate structure formation is achieved, but poly gate spacers and shallow trench isolation are eroded
Solution Approach 1:
The patent segments the hard mask removal process into two distinct stages: first removing the dielectric hard mask layer, then selectively removing the polysilicon hard mask layer. This segmentation allows each mask layer to be removed with appropriate selectivity, preventing erosion of sensitive structures like poly gate spacers and shallow trench isolation while maintaining manufacturing precision for gate structure formation.
Solution Approach 2:
The patent introduces an intermediary polysilicon hard mask layer between the dielectric hard mask and the poly gate structure. This intermediary layer serves as a protective buffer during etching processes, preventing direct contact between aggressive etchants and sensitive structures, thereby eliminating erosion while enabling precise gate structure formation.
2Manufacturing precision
If ion-implantation is used for polysilicon gate doping, then doping is achieved, but impurities are introduced into source and drain regions
Solution Approach 1:
The patent uses the polysilicon hard mask layer as an intermediary barrier during ion-implantation doping. This layer blocks dopant ions from reaching the source and drain regions while allowing doping of the polysilicon gate. The selective removal of this intermediary layer after doping achieves precise doping control without introducing harmful impurities into adjacent regions.
Solution Approach 2:
The patent performs preliminary patterning to create the polysilicon hard mask layer before doping. This preliminary structure serves as a self-aligned mask that defines the doping region precisely, ensuring that dopants are introduced only where needed in the polysilicon gate while preventing contamination of source and drain regions.
3Productivity
If device geometry is reduced to increase circuit density, then more devices per wafer are achieved, but process limitations are encountered
Solution Approach 1:
The patent segments the mask and doping processes into distinct, manageable stages with clear separation of functions. This segmentation simplifies each individual process step, making them more controllable and less prone to failure at reduced geometries, thereby enabling higher circuit density without proportionally increasing process complexity.
Solution Approach 2:
The polysilicon hard mask layer serves multiple functions: it acts as a protective barrier during dielectric removal, serves as a self-aligned mask for source/drain etching, and provides a doping mask for polysilicon gate doping. This multi-functionality reduces the need for additional separate process steps, maintaining process simplicity while achieving high device density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device yields, maintains compatibility with conventional processes, and improves polysilicon gate doping properties, particularly for 90 nanometer design rules and below, while increasing hole mobility and reducing impurity introduction into source and drain regions.
Implementation Method 1
plasma etching to expose the polysilicon gate for doping
Implementation Method 2
introducing dopant impurities into the polysilicon gate structure using at least an implantation process
Data Source
AI summary
A method of fabricating an integrated circuit including strained silicon bearing regions. The method forms a blanket layer of material having an initial thickness overlying a source region, a drain region, and a gate structure of an MOS device to cover an upper surface of the gate structure, including the hard mask layer, to form a substantially planarized surface region from the blanket layer. The method removes a portion of the initial thickness of the blanket layer to remove the hard mask and expose a portion of the gate structure. In a preferred embodiment, the portion of the gate structure is substantially polysilicon material. The method introduces dopant impurities into the portion of the gate structure using at least an implantation process to dope the gate structure, while maintaining the source region and the drain region free from the dopant impurities.