Strained Silicon MOS Transistors Using Silicon Germanium Source Drain
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Solution Overview
Problem
Conventional integrated circuit manufacturing processes face limitations in reducing device size and achieving faster switching speeds while maintaining clear signal transmission, particularly in MOS device designs, which are complex and difficult to manufacture.
Innovation Solution
The method involves forming strained silicon structures by depositing silicon germanium material into recessed regions of MOS devices, causing the channel region to be in a compressive mode, which enhances performance without requiring substantial modifications to existing equipment or processes, and is compatible with conventional technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device size is reduced to increase circuit density, then more devices can be fabricated on each wafer, but manufacturing precision and signal clarity become more difficult to maintain
Solution Approach 1:
The patent applies parameter changes by introducing silicon germanium material with different lattice constants into the source and drain regions, creating compressive strain in the channel region. This material parameter change enables improved hole mobility and device performance at reduced geometry sizes without compromising manufacturing precision, as the strain effect compensates for the challenges of smaller feature sizes
Solution Approach 2:
The patent implements local quality by selectively depositing silicon germanium material only in the source and drain regions adjacent to the channel, while leaving the channel region itself with strained silicon. This localized material differentiation creates compressive strain exactly where needed to improve hole mobility, without affecting other parts of the device, thus maintaining manufacturing precision while enabling smaller device features
2Speed
If device size is reduced to achieve faster switching speeds, then performance improves, but maintaining clear signals for switching becomes more difficult
Solution Approach 1:
The patent changes the material parameter by introducing silicon germanium with larger lattice spacing into the source and drain regions, creating compressive strain in the channel. This strain parameter change directly improves hole mobility and switching speed while maintaining signal clarity, as the strained silicon channel preserves good interface quality and carrier transport properties even at reduced device dimensions
3Productivity
If conventional MOS device designs are used to reduce device size, then circuit density increases, but manufacturing complexity and difficulty increase
Solution Approach 1:
The patent applies preliminary action by forming the silicon germanium source and drain regions before final gate patterning and before forming the second sidewall spacers. This sequence allows the strain-induced-compression-effect to be established early in the process, simplifying subsequent manufacturing steps and reducing overall process complexity while enabling device miniaturization
Solution Approach 2:
The patent uses sidewall spacer structures as intermediary elements that mediate between the gate structure and the source/drain regions. The first sidewall spacers are formed using deposited material, and the second sidewall spacers are formed using etched portions of the first spacers. These intermediary spacer structures simplify the manufacturing process by providing self-aligned references for subsequent steps, reducing complexity while enabling smaller device features
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases device yields, supports design rules of 90 nanometers and less, and improves hole mobility in CMOS devices, providing a more efficient and integrated process for semiconductor wafer fabrication.
Implementation Method 1
depositing silicon germanium material into the source region and the drain region to fill the etched source region and the etched drain region. The method causes a channel region between the source region and the drain region to be strained in compressive mode from at least the silicon germanium material formed in the source region and the drain region
Data Source
AI summary
A method for forming a CMOS semiconductor wafer. The method includes providing a semiconductor substrate (e.g., silicon wafer) and forming a dielectric layer (e.g., silicon dioxide, silicon oxynitride) overlying the semiconductor substrate. The method includes forming a gate layer overlying the dielectric layer and patterning the gate layer to form a gate structure including edges. The method includes forming a dielectric layer overlying the gate structure to protect the gate structure including the edges. Preferably, the dielectric layer has a thickness of less than 40 nanometers. The method includes etching a source region and a drain region adjacent to the gate structure using the dielectric layer as a protective layer and depositing silicon germanium material into the source region and the drain region to fill the etched source region and the etched drain region. The method causes a channel region between the source region and the drain region to be strained in compressive mode from at least the silicon germanium material formed in the source region and the drain region. The method includes forming a second protective layer overlying surfaces and performing an anisotropic etching process to form spacer structures to seal the gate structure.