Strained-Silicon MOSFET Structure for Low-Defect SiGe Isolation
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Solution Overview
Problem
The manufacturing of semiconductor devices with strained silicon layers faces challenges such as increased defects, leakage currents, and reliability issues due to lattice mismatches and stress in silicon germanium layers, which complicate the formation of isolation and source/drain regions, leading to suboptimal transistor performance.
Innovation Solution
A semiconductor device structure is developed with a graded silicon germanium layer and a relaxed silicon germanium layer, where the germanium concentration in the first silicon germanium layer increases from the lower to the upper portion, and the strained silicon layer is formed on this layer with a thickness between 1,000 Å to 5,000 Å, allowing for controlled formation of an isolation layer and source/drain regions without exposing the underlying silicon germanium layer, thereby reducing defects and improving etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the thickness of the strained silicon layer is increased to grow on a high-germanium silicon germanium layer, then the bonding distance between silicon atoms is increased improving electron or hole mobility, but the stress in the strained silicon layer is considerably increased leading to strain relaxation and crystalline structure breakdown
Solution Approach 1:
The silicon germanium layer is divided into multiple layers with different germanium concentrations. The first silicon germanium layer has a lower germanium concentration (0-15 at%) and the second silicon germanium layer has a higher germanium concentration (15-30 at%). This segmentation allows the strained silicon layer to be grown on a layer with controlled stress characteristics, preventing strain relaxation while maintaining the desired bonding distance for high mobility.
Solution Approach 2:
The germanium concentration parameter in the silicon germanium layer is optimized to a specific range (15-30 at%) to achieve the desired balance. By controlling the germanium concentration within this range, the lattice parameter is adjusted to provide adequate bonding distance for high carrier mobility while keeping the stress below the threshold that causes strain relaxation.
2Speed
If the germanium content of the silicon germanium layer is increased to increase the bonding distance between silicon atoms, then the mobility of electrons or holes is improved, but the lattice mismatches of the silicon germanium layer are increased leading to more defects
Solution Approach 1:
The silicon germanium layer is segmented into two distinct layers with different germanium concentrations. The first layer has lower germanium content (0-15 at%) providing a transition zone with fewer lattice mismatches, while the second layer has higher germanium content (15-30 at%) providing the desired bonding distance. This segmentation reduces overall defect density while maintaining high mobility.
Solution Approach 2:
Different regions of the silicon germanium layer have different germanium concentrations optimized for different functions. The lower-germanium region provides a buffer against lattice mismatches, while the higher-germanium region provides the bonding distance needed for high mobility. This local quality variation allows optimization of both defect density and carrier mobility.
3Manufacturing precision
If the strained silicon layer is grown on a silicon germanium layer with high germanium content to achieve greater thickness, then the bonding distance is increased improving mobility, but the etching, cleaning and diffusion processes become complicated due to different characteristics of silicon germanium layer
Solution Approach 1:
The silicon germanium layer is segmented into two layers with different germanium concentrations, which have different etching rates. The first layer (lower germanium) and second layer (higher germanium) can be selectively etched at different rates, allowing for simplified process control. The isolation layer can be formed to a controlled depth without exposing the substrate, simplifying the overall fabrication process.
Solution Approach 2:
The germanium concentration parameter is changed across the silicon germanium layer structure, creating a gradient or stepped structure. This parameter variation allows for controlled etching behavior, where the etch rate changes predictably through the different layers, simplifying the formation of isolation structures and source/drain regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and electrical characteristics of semiconductor devices by minimizing lattice dislocations, reducing leakage currents, and improving the yield and response speed of transistors, while maintaining proper electrical isolation and reducing the risk of transistor failure.
Implementation Method 1
a first silicon germanium layer (102) having a concentration gradient of germanium formed on a single crystalline silicon substrate (100)
Implementation Method 2
a strained silicon layer (106) formed on the second silicon germanium layer (104)... the strained silicon layer may have a bonding distance between silicon atoms which is larger than a bonding distance between silicon atoms of a conventional single crystalline silicon layer
Data Source
AI summary
A semiconductor device formed on a strained silicon layer and a method of manufacturing such a semiconductor device are disclosed. In accordance with this invention, a first silicon germanium layer is formed on a single crystalline silicon substrate; a second silicon germanium layer is formed on the first silicon germanium layer, the second silicon germanium layer having a concentration of germanium in a range of about 1 percent by weight to about 15 percent by weight based on the total weight of the second silicon germanium layer; a strained silicon layer is formed on the second silicon germanium layer; an isolation layer is formed at a first portion of the strained silicon layer; a gate structure is formed on the strained silicon layer; and, source/drain regions are formed at second portions of the strained silicon layer adjacent to the gate structure to form a transistor.