Strained Silicon MOSFET Stress Engineering
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Solution Overview
Problem
Current semiconductor manufacturing technologies face challenges in achieving high response speed and integration for both N-typed and P-typed MOSFETs on a single silicon substrate due to differences in stress levels in the channel regions, which hinder the formation of effective PMOS transistors with strong tensile stress.
Innovation Solution
A method involving the formation of gate electrodes and source/drain regions with specific stresses, using selective epitaxial growth to create patterns with compressive stress for PMOS transistors, and thermal treatment to enhance tensile stress in NMOS transistors, allowing for the simultaneous manufacturing of NMOS and PMOS transistors with improved characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If additional processes are executed to obtain PMOS transistor with compressive stress, then the manufacturing complexity increases, but the transistor characteristics are improved
Solution Approach 1:
The patent combines the formation of NMOS and PMOS transistors into a unified manufacturing process flow. By forming both transistor types in sequence on the same substrate using integrated process steps including selective epitaxial growth and coordinated stress layer formation, the patent achieves improved PMOS characteristics without requiring separate, additional manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process and enhances the response speed of both NMOS and PMOS transistors by applying tensile and compressive stresses respectively, leading to improved electrical characteristics and high integration capabilities.
Implementation Method 1
the channel of the MOSFET may be formed in a strained silicon layer so that the mobility of electrons or holes in the channel may be enhanced. The strained silicon layer may include silicon atoms having extended bonding length or compressed bonding length.
Implementation Method 2
forming patterns having a second stress in the recesses
Implementation Method 3
a thermal treatment process is performed about the substrate so that a channel region of the transistor has a relatively strong tensile stress
Data Source
AI summary
In a method of manufacturing a semiconductor device, a first gate electrode and a second gate electrode are formed in a first area and a second area of a substrate. Non-crystalline regions are formed in the first area of the substrate adjacent the first gate electrode. A layer having a first stress is formed on the substrate and the first and the second gate electrodes. A mask is formed on a first portion of the layer in the first area of the substrate to expose a second portion of the layer in the second area. The second portion is etched to form a sacrificial spacer on a sidewall of the second gate electrode. The second area of the substrate is partially etched using the mask, the second gate electrode and the sacrificial spacer, to form recesses in the second area of the substrate adjacent the second gate electrode. Patterns having a second stress are formed in the recesses.