Strained Silicon Nitride Capping Layer for Non-Volatile Memory
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Solution Overview
Problem
Flash memory cell technologies face scaling limitations due to high voltage requirements for program and erase operations, making it difficult to maintain an acceptable aspect ratio as MOSFETs are scaled to deep sub-micron dimensions, limiting performance and scalability.
Innovation Solution
A non-volatile memory cell with a tensile strained silicon layer is fabricated, featuring a substrate with doped source/drain regions, a tunnel dielectric, a charge storage gate, an inter-gate dielectric, and a control gate with a stressed silicon nitride capping layer, which introduces tensile stress to improve electron mobility without shrinking transistor size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOSFETs are scaled to deep sub-micron dimensions to increase memory density and speed, then device size is reduced, but it becomes difficult to maintain an acceptable aspect ratio and high voltage requirements for program and erase operations cannot be met
Solution Approach 1:
The patent applies parameter changes by introducing tensile strain to the silicon channel through a stressed silicon nitride capping layer. This strain modifies the physical parameters of the silicon lattice, enhancing carrier mobility and allowing the device to maintain acceptable electrical characteristics even at deep sub-micron dimensions where traditional scaling would fail to maintain proper aspect ratio and voltage requirements.
Solution Approach 2:
The patent uses a composite structure consisting of a silicon channel layer combined with a stressed silicon nitride capping layer. This composite material system allows the thin silicon channel to achieve enhanced carrier mobility through mechanical strain from the nitride layer, enabling deep sub-micron transistors to maintain proper electrical characteristics without requiring larger physical dimensions.
2Area of moving object
If transistor size is reduced to increase memory density, then power consumption decreases, but performance and scalability are limited due to scaling limitations
Solution Approach 1:
The patent changes the physical state of the silicon channel by introducing tensile strain through the stressed silicon nitride layer. This parameter change enhances carrier mobility in the silicon lattice, allowing smaller transistors to achieve higher drive currents and faster switching speeds, thereby improving memory performance and scalability without increasing device size.
Solution Approach 2:
The patent applies local quality by introducing strain specifically in the channel region where charge carriers flow. The stressed silicon nitride capping layer is positioned to induce tensile strain locally in the silicon channel, enhancing carrier mobility precisely where needed for current flow, while other regions of the device maintain their normal structural properties.
3Length of moving object
If gate oxide thickness is scaled to less than 10 nm to maintain aspect ratio in sub-micron devices, then device density increases, but depletion region width and junction depth must also be scaled to smaller dimensions making fabrication more difficult
Solution Approach 1:
The patent applies parameter changes by introducing tensile strain to the silicon channel, which enhances carrier mobility and allows the device to achieve acceptable electrical characteristics with thinner gate oxides. This strain modification compensates for the reduced dimensions, enabling gate oxide thickness to be scaled to less than 10 nm while maintaining proper device performance without requiring proportional scaling of all other dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The strained silicon nitride layer enhances electron mobility, resulting in faster memory devices with lower electric fields and drain voltages, improving channel hot electron efficiency, read operations, and data access times while maintaining device performance.
Implementation Method 1
The stressed silicon nitride layer is formed over the control gate to improve the mobility of channel hot electrons
Data Source
AI summary
A non-volatile memory device has improved performance from a stressed, silicon nitride capping layer. The device is comprised of memory cells in a substrate that have source and drain regions. A tunnel dielectric is formed over the substrate between each pair of source and drain regions. If the memory device is an NROM, a nitride charge storage layer is formed over the tunnel dielectric. If the memory device is a flash memory, a floating gate is formed over the tunnel dielectric. An inter-gate insulator and control gate are then formed over the charge storage layer. The stressed, silicon nitride capping layer is formed over the control gate.