Strained Silicon Layer Stress Retention via Epitaxial Replacement
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Solution Overview
Problem
Conventional methods for forming semiconductor devices with strained silicon layers face challenges in maintaining stress integrity due to thermal processes like thermal oxidation and annealing, which can cause defects and loss of stress in the strained silicon layer.
Innovation Solution
A method is introduced where a first strained silicon layer is removed after forming a shallow trench isolation, and a second strained silicon layer with the same lattice constant is formed to replace it, ensuring the predetermined stress is maintained by using epitaxial layers with graded germanium concentration and selective epitaxial growth to replicate the original stress conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If thermal oxidation process or annealing process is performed during STI formation, then the semiconductor device can be manufactured with standard工艺流程, but the stress in the strained silicon layer is lost and defects such as dislocations occur
Solution Approach 1:
The patent applies preliminary action by forming the strained silicon layer before the thermal oxidation process. The strained silicon layer is created on a SiGe buffer layer, establishing the stress state before any thermal processes that would cause stress loss occur during subsequent manufacturing steps.
Solution Approach 2:
The patent segments the manufacturing process into distinct stages: first forming the SiGe buffer layer, then forming the strained silicon layer, and finally performing the thermal oxidation process for STI formation. This segmentation allows the stressed layer to be created before exposure to thermal processes that would compromise its integrity.
2Length of moving object
If the scale of gate, source and drain is decreased to achieve miniaturization, then the critical dimension is reduced, but the carrier mobility decreases due to physical material limitations
Solution Approach 1:
The patent changes the physical parameter of the silicon layer by introducing strain through the SiGe buffer layer. This parameter change (from unstrained to strained silicon) fundamentally alters the material properties, enabling higher carrier mobility even at reduced critical dimensions for miniaturized transistors.
Solution Approach 2:
The patent uses a composite structure combining SiGe buffer layer and silicon layer. The SiGe layer with different lattice constant provides the strain necessary to enhance carrier mobility in the overlying silicon layer, allowing the device to maintain performance despite size reduction.
3Reliability
If a strained silicon layer is formed on SiGe layer to provide biaxial tensile stress, then carrier mobility is increased, but subsequent thermal processes cause stress loss and defects
Solution Approach 1:
The strained silicon layer is formed in advance before any thermal oxidation or annealing processes. This preliminary formation ensures the stress is established before exposure to thermal budgets that would otherwise cause stress relaxation or loss in subsequent manufacturing steps.
Solution Approach 2:
The patent provides beforehand cushioning by creating the strained silicon layer structure prior to thermal processes. This preparatory structure is designed to withstand or protect against the effects of subsequent thermal oxidation and annealing processes that would otherwise compromise the stress integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively sustains the stress of the strained silicon layer, enhancing the reliability and performance of semiconductor devices by preventing stress loss and defects caused by subsequent semiconductor processes.
Implementation Method 1
The lattice constant of silicon (Si) is 5.431 angstroms (A), and the lattice constant of germanium (Ge) is 5.646 A. When the silicon layer is disposed on the SiGe layer, lateral stress is formed in the silicon layer due to the lattice constant difference
Implementation Method 2
The strained silicon layer facilitates the formation of a gate dielectric layer of high quality, and provides stress to the channel region of a transistor for enhancing carrier mobility
Implementation Method 3
The excessive thermal budget from other semiconductor process such as a thermal oxidation process performed during the formation of shallow trench isolations (STI)
Implementation Method 4
a silicon layer is further formed on the SiGe layer to constitute the strained semiconductor substrate
Data Source
AI summary
A method of forming a semiconductor device includes the following steps. A semiconductor substrate having a first strained silicon layer is provided. Then, an insulating region such as a shallow trench isolation (STI) is formed, where a depth of the insulating region is substantially larger than a depth of the first strained silicon layer. Subsequently, the first strained silicon layer is removed, and a second strained silicon layer is formed to substitute the first strained silicon layer.