Strained Silicon Transistor Faceting Prevention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Faceting and voids occur during epitaxial growth of silicon compounds like SiGe or SiC near oxide boundaries, disrupting crystal growth and requiring techniques to suppress these defects for improved transistor performance.
Innovation Solution
Lining isolation trenches with silicon nitride (SiN) to create a barrier between the oxide and the epitaxial growth region, preventing faceting by establishing nitride-silicon boundaries instead of oxide-silicon interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If epitaxial growth is performed adjacent to oxide boundaries, then isolation trenches can be filled with oxide, but faceting and voids occur during crystal growth
Solution Approach 1:
A silicon nitride liner is deposited as an intermediary layer between the oxide isolation trench and the epitaxial silicon compound growth region. This liner prevents direct contact between the oxide boundary and the epitaxial layer, eliminating the faceting effect while allowing oxide to remain in the isolation trench for ease of manufacture.
2Manufacturing precision
If silicon barriers are used to prevent faceting, then epitaxial growth quality improves, but circuit density decreases due to real estate loss
Solution Approach 1:
Instead of using wide silicon barriers that reduce circuit density, a thin silicon nitride liner is applied locally at the interface between the isolation trench and epitaxial region. This localized approach provides the necessary faceting prevention while minimizing area consumption and maintaining high circuit density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents faceting and voids, maintaining circuit density and enhancing epitaxial growth quality without the real estate loss associated with silicon barriers, ensuring facet-free epitaxial source/drain transistors with improved charge mobility.
Implementation Method 1
Epitaxial growth refers to growth of a layer on the silicon surface that has a similar crystalline structure to that of the underlying bulk silicon
Data Source
AI summary
The presence of a facet or a void in an epitaxially grown crystal indicates that crystal growth has been interrupted by defects or by certain material boundaries. Faceting can be suppressed during epitaxial growth of silicon compounds that form source and drain regions of strained silicon transistors. It has been observed that faceting can occur when epitaxial layers of certain silicon compounds are grown adjacent to an oxide boundary, but faceting does not occur when the epitaxial layer is grown adjacent to a silicon boundary or adjacent to a nitride boundary. Because epitaxial growth of silicon compounds is often necessary in the vicinity of isolation trenches that are filled with oxide, techniques for suppression of faceting in these areas are of particular interest. One such technique, presented herein, is to line the isolation trenches with SiN to provide a barrier between the oxide and the region in which epitaxial growth is intended.