Strained Silicon Structure with Variable Source-Drain Distances
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Solution Overview
Problem
The miniaturization of Si semiconductor elements, such as MOSFETs, has reached a limit due to carrier mobility approaching theoretical values, and the use of strained silicon layers with different recess shapes in high and low density regions leads to varying stress levels, affecting device performance.
Innovation Solution
A strained silicon structure is designed with transistors in high and low density regions having different source/drain to gate distances, resulting in varying channel strains to optimize performance across both regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the same etching step is used to form recesses in both high density region and low density region, then the manufacturing process is simple, but the channel strain becomes non-uniform due to different device densities
Solution Approach 1:
The patent applies local quality by forming recesses with different depths in high density regions versus low density regions. Specifically, the recesses in the high density region are formed to a first depth, while the recesses in the low density region are formed to a second depth that is greater than the first depth. This allows each region to receive appropriate strain levels according to its device density requirements, resolving the contradiction between manufacturing simplicity and strain uniformity.
2Manufacturing precision
If deeper recesses are formed in low density region to compensate for lower device density, then channel strain is improved in low density region, but the manufacturing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the etching process into multiple stages with different etching conditions for different regions. The method includes forming a first set of recesses in the high density region with first etching conditions, then forming a second set of recesses in the low density region with second etching conditions that create greater depth. This segmented approach achieves uniform channel strain across regions while managing manufacturing complexity through systematic process division.
3Speed
If carrier mobility is increased to reach theoretical values through miniaturization, then device performance improves, but further performance enhancement becomes difficult
Solution Approach 1:
The patent applies parameter changes by introducing mechanical strain as a new parameter to enhance carrier mobility beyond what miniaturization alone can achieve. By forming recesses with controlled depths in different regions and growing strained silicon layers, the patent creates tensile or compressive strain in the channel, which modifies the band structure and increases carrier mobility. This allows continued performance enhancement even when miniaturization effects are diminishing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the overall performance of the semiconductor device by controlling channel strain, ensuring higher strain in high density regions and maintaining adequate operational performance in both regions.
Implementation Method 1
the stress provided by the SiGe layer will be different between the high density region and the low density region
Implementation Method 2
attempts have been made to use a strained silicon (Si) layer grown epitaxially on a Si wafer with a silicon germanium (SiGe) layer in a recess in the substrate
Data Source
AI summary
A strained silicon substrate structure includes a first transistor and a second transistor disposed on a substrate. The first transistor includes a first gate structure and two first source/drain regions disposed at two sides of the first gate structure. A first source/drain to gate distance is between each first source/drain region and the first gate structure. The second transistor includes a second gate structure and two source/drain doped regions disposed at two side of the second gate structure. A second source/drain to gate distance is between each second source/drain region and the second gate structure. The first source/drain to gate distance is smaller than the second source/drain to gate distance.