Strained Silicon Transistor Via Interconnects for 3D IC Density
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Solution Overview
Problem
The semiconductor industry faces limitations in increasing circuit density beyond two-dimensional integration due to physical constraints, necessitating the development of three-dimensional integrated circuits (3D ICs) with effective electrical connections between stacked dies.
Innovation Solution
The formation of connections between strained silicon transistors and through vias in 3D ICs involves a process that includes forming shallow trench isolations, epitaxially growing strained silicon terminals, and using through silicon vias to connect dies, with a contact etch stop layer and multiple inter-layer dielectric layers to enhance carrier mobility and electrical coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If two-dimensional integration is continued to improve circuit density, then manufacturing processes can be maintained, but physical limits prevent further density increases
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional vertical integration by stacking multiple semiconductor dies. Through-silicon vias (TSVs) enable vertical interconnections between stacked dies, allowing circuit density to increase by utilizing the third dimension (depth) rather than being constrained to the two-dimensional surface plane.
2Reliability
If through vias are formed by etching and filling with conductive material, then electrical connections between stacked dies are achieved, but process complexity increases
Solution Approach 1:
The patent forms the conductive fill material for through-silicon vias before completing the via etching process. This preliminary filling action, followed by subsequent etching steps, simplifies the overall via formation process by avoiding the need for complex in-situ filling techniques and enables better control over via dimensions and conductivity.
3Reliability
If conventional silicon transistors are used, then manufacturing is straightforward, but carrier mobility is limited
Solution Approach 1:
The patent employs strained silicon technology where mechanical stress is applied to the silicon crystal lattice during fabrication. This strain modifies the band structure of silicon, increasing carrier mobility by approximately 50-70% compared to conventional unstrained silicon, while remaining compatible with existing CMOS manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables increased carrier mobility and improved electrical connectivity between stacked dies, enhancing the performance and density of 3D ICs by applying mechanical stress and leveraging strained silicon technology.
Implementation Method 1
apply mechanical stress to the channel of a transistor to increase the carrier mobility
Implementation Method 2
electrical connections are formed between each die and contact pads on a substrate
Data Source
AI summary
Methods and devices for connecting a through via and a terminal of a transistor formed of a strained silicon material are provided. The terminal, which can be a source or a drain of a NMOS or a PMOS transistor, is formed within a substrate. A first contact within a first inter-layer dielectric (ILD) layer over the substrate is formed over and connected to the terminal. A through via extends through the first ILD layer into the substrate. A second contact is formed over and connected to the first contact and the through via within a second ILD layer and a contact etch stop layer (CESL). The second ILD layer is over the CESL, and the CESL is over the first ILD layer, which are all below a first inter-metal dielectric (IMD) layer and the first metal layer of the transistor.