Semiconductor Heterostructure Strained Smoothing Layer
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Solution Overview
Problem
Existing semiconductor heterostructures face issues with surface roughness and topology, leading to defects and poor bonding during wafer transfer processes, particularly due to thermal treatments required for insulator layer formation, which can cause unintended diffusion and thickness non-uniformities.
Innovation Solution
A strained smoothing layer with an in-plane lattice parameter between the substrate and top layer parameters is introduced, allowing direct bonding without an insulator layer, reducing thermal load and improving surface roughness through lower growth temperatures and specific composition adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thermal treatment is applied to form an insulator layer on the donor wafer, then bonding capability is improved, but thermal diffusion and interface degradation occur
Solution Approach 1:
The patent removes the insulator layer formation step from the donor wafer processing, extracting the thermal treatment that causes harmful diffusion. Instead, direct bonding is performed between the top layer and handle wafer, eliminating the source of thermal damage while maintaining bonding capability through surface preparation alone.
Solution Approach 2:
The patent performs preliminary surface preparation on the top layer through CMP and chemical treatment before bonding, creating a bonding-ready surface without thermal treatment. This preliminary action ensures bonding capability is achieved without subsequent thermal diffusion issues.
2Manufacturing precision
If the surface roughness is reduced through additional CMP steps, then bonding quality is improved, but the thickness of the top layer is reduced below critical values
Solution Approach 1:
The patent performs the CMP step preliminarily on the graded buffer layer and ungraded layer before depositing the final top layer. This ensures the surface is smoothed in advance, allowing the top layer to be deposited on a smooth surface without requiring additional thinning that would compromise its critical thickness.
3Manufacturing precision
If the growth temperature is reduced to improve surface roughness, then surface quality is improved, but growth rate decreases
Solution Approach 1:
The patent performs the low-temperature growth step preliminarily to form the ungraded layer with improved surface roughness characteristics. This preliminary low-temperature growth creates a smooth foundation that allows subsequent top layer deposition to proceed with acceptable rates without compromising the surface quality already established.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces surface roughness and enhances bonding quality, preventing defects and maintaining sharp interfaces, thus enabling high-quality wafer splitting and transfer with reduced thermal stress.
Implementation Method 1
forming on the graded buffer layer an ungraded layer of a semiconductor material; forming on the ungraded layer a top layer of a semiconductor material
Implementation Method 2
bonding the donor wafer with the handle wafer
Data Source
Figure 1a~1g
Figure 2a~2f
Figure 3a~3g
AI summary
The invention relates to a method of manufacturing a semiconductor heterostructure, comprising manufacturing a donor wafer, comprising providing a first substrate with a first in-plane lattice parameter, providing on the first substrate a spatially graded buffer layer having on top in a relaxed state a second in-plane lattice parameter, forming on the graded buffer layer an ungraded layer of a semiconductor material having in a relaxed state a third in-plane lattice parameter, forming on the ungraded layer a top layer of a semiconductor material, and manufacturing a handle wafer, comprising providing a second substrate, forming on the second substrate an insulator layer, and bonding the donor wafer with the handle wafer. It is the object of the invention to reduce the thermal load on the donor wafer substrate with the top layer before bonding and to achieve nevertheless good bonding results. The object is solved by a method of the above mentioned type according to which said ungraded layer is a strained smoothing layer wherein the third in-plane lattice parameter of this strained smoothing layer is between the first and second lattice parameter, and said handle wafer is bonded with the donor wafer in such way that the insulator layer of the handle wafer is bonded directly onto the free surface of the top layer of the donor wafer, or the insulator layer of the handle wafer is bonded onto a superficial layer being present on the surface of the top layer of the donor wafer, said superficial layer having a thickness being equal to or smaller than 10 nanometres.