Strained-SOI Substrate Local Strain Engineering for NMOS PMOS Mobility
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Simultaneously improving carrier mobility for both NMOS and PMOS transistors on uniformly-strained substrates is challenging due to different strain optimization requirements for each type.
Innovation Solution
A semiconductor fabrication process that alters strain characteristics in biaxially-strained SOI substrates by amorphizing and annealing specific regions to create different strain conditions for each type of transistor, allowing for the fabrication of NMOS and PMOS transistors with optimized performance characteristics without altering their layout or threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a uniformly-strained substrate is used, then one type of transistor (NMOS or PMOS) achieves optimized carrier mobility, but the other type cannot achieve optimal performance
Solution Approach 1:
The patent applies local quality by creating different strain conditions in different regions of the substrate. Specifically, it forms a first region with first strain characteristics optimized for NMOS transistors and a second region with second strain characteristics optimized for PMOS transistors. This allows each transistor type to be fabricated in its optimized strain environment without compromising the other type's performance.
Solution Approach 2:
The substrate is segmented into multiple regions with different strain characteristics. The patent divides the substrate into a first region and a second region, where each region has tailored strain properties suitable for specific transistor types. This segmentation enables simultaneous optimization of both NMOS and PMOS devices on the same substrate.
2Reliability
If different strain conditions are created for different transistor types, then both NMOS and PMOS achieve optimized performance, but the fabrication process becomes more complex
Solution Approach 1:
The patent employs preliminary action by forming the different strain regions in the substrate before fabricating the transistors. The strain characteristics are established in advance, allowing subsequent transistor fabrication to proceed with standard processes without requiring additional complexity for strain management during device formation.
Solution Approach 2:
The patent utilizes parameter changes by modifying the strain characteristics of the substrate regions through controlled amorphization and annealing processes. By changing the physical and chemical parameters of the substrate (creating amorphous regions and controlling recrystallization), distinct strain environments are achieved without fundamentally altering the fabrication workflow for the transistors themselves.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the fabrication of transistors with improved carrier mobility by creating distinct strain conditions for each type, optimizing NMOS:PMOS ratios and performance characteristics without requiring layout changes or threshold voltage adjustments.
Implementation Method 1
A portion of the second region is amorphized to form amorphous semiconductor in the second region
Implementation Method 2
The wafer may then be annealed to re-crystallize the amorphous semiconductor
Data Source
AI summary
A semiconductor fabrication process preferably used with a semiconductor on insulator (SOI) wafer. The wafer's active layer is biaxially strained and has first and second regions. The second region is amorphized to alter its strain component(s). The wafer is annealed to re-crystallize the amorphous semiconductor. First and second types of transistors are fabricated in the first region and the second region respectively. Third and possibly fourth regions of the active layer may be processed to alter their strain characteristics. A sacrificial strain structure may be formed overlying the third region. The strain structure may be a compressive. When annealing the wafer with the strain structure in place, its strain characteristics may be mirrored in the third active layer region. The fourth active layer region may be amorphized in stripes that run parallel to a width direction of the transistor strain to produce uniaxial stress in the width direction.