Strained SOI via Elastic Edge Relaxation of Stressed Buried Insulator
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Solution Overview
Problem
Conventional methods for creating strained silicon on insulator devices face challenges such as high dislocation density and ineffective strain induction in the silicon active region, leading to undesirable consequences like source/drain junction leakage and reduced mobility in MOSFETs.
Innovation Solution
The method involves etching trenches through a stressed buried insulator structure into a semiconductor on insulator substrate, inducing strain in the surface semiconductor layer through edge relaxation, and using ion implantation to control stress within the buried insulator, thereby creating strained active regions with reduced dislocation density and improved mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a thick layer of SiGe is grown to provide strain relaxation, then the in-plane lattice parameter increases to enable strained silicon growth, but high dislocation density is generated in the SiGe layer
Solution Approach 1:
The patent divides the SiGe layer into multiple thin sub-layers separated by SiO2 spacer layers. Each SiGe sub-layer is thinner than the critical thickness for dislocation formation, so they remain in a strained state without generating misfit dislocations. The SiO2 layers prevent strain relaxation while allowing the overall structure to achieve the required in-plane lattice parameter expansion for strained silicon growth.
Solution Approach 2:
The SiO2 spacer layers act as intermediary elements between the SiGe layers. These spacers have different mechanical and thermal properties that allow them to accommodate the lattice mismatch without forming dislocations, while still transmitting the necessary strain to the overlying silicon layer. The SiO2 layers serve as a mediator that decouples the strain relaxation mechanism from dislocation formation.
2Stability of the object's composition
If the SiGe layer thickness exceeds the critical thickness, then strain relaxation occurs, but threading dislocations propagate through the overlying strained silicon layer causing device defects
Solution Approach 1:
By segmenting the SiGe layer into multiple thin sub-layers, each sub-layer remains below the critical thickness for dislocation formation. This prevents the nucleation of misfit dislocations at the SiGe/SiO2 interfaces, thereby eliminating the source of threading dislocations that would otherwise propagate through the silicon channel.
Solution Approach 2:
The SiO2 spacer layers are inserted beforehand between the SiGe sub-layers to prevent strain relaxation. This prior cushioning approach ensures that the SiGe layers remain in a strained state without exceeding the critical thickness, thereby preventing dislocation formation before it can occur.
3Ease of manufacture
If conventional SOI wafers with non-stressed BOX layers are used, then manufacturing is simpler, but strain cannot be effectively induced in the silicon active region
Solution Approach 1:
The patent changes the stress state parameter of the BOX layer from unstressed to stressed. By depositing the SiGe layers with controlled stress parameters and inserting SiO2 spacers at specific intervals, the BOX layer is put into a stressed state that can be elastically relaxed to induce strain in the silicon active region without requiring thick SiGe layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively induces strain in the surface semiconductor layer, enhancing mobility and reducing defects, resulting in improved performance and reliability of MOSFETs while maintaining low defect densities and cost-effectiveness.
Implementation Method 1
etching through the surface semiconductor layer, the stressed buried insulator structure and into the base substrate... causes in-plane strain in the surface semiconductor layer... induced by elastic edge relaxation
Implementation Method 2
implanting ions into or through the buried insulator structure to induce stress within the buried insulator structure
Data Source
AI summary
An SOI wafer contains a compressively stressed buried insulator structure. In one example, the stressed buried insulator (BOX) may be formed on a host wafer by forming silicon oxide, silicon nitride and silicon oxide layers so that the silicon nitride layer is compressively stressed. Wafer bonding provides the surface silicon layer over the stressed insulator layer. Preferred implementations of the invention form MOS transistors by etching isolation trenches into a preferred SOI substrate having a stressed BOX structure to define transistor active areas on the surface of the SOI substrate. Most preferably the trenches are formed deep enough to penetrate through the stressed BOX structure and some distance into the underlying silicon portion of the substrate. The overlying silicon active regions will have tensile stress induced due to elastic edge relaxation.