Strained Source Drain Structures via Epitaxial Growth
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Solution Overview
Problem
Existing methods for manufacturing integrated circuit devices, particularly MOSFETs, face challenges in achieving optimal transistor performance due to limitations in controlling the geometry and complexity of source and drain features, leading to suboptimal carrier mobility and increased short channel effects.
Innovation Solution
A method involving the formation of doped features in the source and drain regions with specific implantation processes and etching profiles to control the surface proximity and tip depth of recesses, followed by epitaxial growth of silicon or silicon germanium to create strained source and drain features, enhancing carrier mobility and reducing short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional source/drain features are used in scaled-down MOSFETs, then manufacturing process remains simple, but carrier mobility is suboptimal and short channel effects increase
Solution Approach 1:
The patent applies local quality by introducing strained semiconductor material specifically in the source and drain regions adjacent to the channel, while keeping the rest of the device structure conventional. This localized strain enhancement improves carrier mobility in the critical transport regions without requiring complex strained structures throughout the entire device, thus resolving the contradiction between device performance and structural complexity.
Solution Approach 2:
The patent changes the material parameter by using epitaxially grown strained semiconductor material with different crystal orientation or composition compared to conventional source/drain. This parameter change induces mechanical strain in the channel region, enhancing carrier mobility and reducing short channel effects, thereby improving device performance without significantly increasing manufacturing complexity.
2Reliability
If epitaxial growth is used to form strained source/drain features, then carrier mobility is enhanced, but manufacturing process complexity increases
Solution Approach 1:
The patent segments the source/drain formation process into distinct epitaxial growth stages, allowing selective strain introduction in specific regions. By dividing the manufacturing process into manageable segments with controlled epitaxial growth, the patent achieves enhanced carrier mobility through strain while maintaining reasonable manufacturing complexity through systematic process organization.
3Productivity
If source/drain geometry is scaled down, then functional density increases, but control over etching profile and surface proximity becomes difficult
Solution Approach 1:
The patent applies preliminary action by performing preparatory steps before the main etching process to establish favorable conditions for profile control. This includes forming sacrificial layers, applying protective coatings, or pre-defining geometric constraints that guide the subsequent etching process, enabling precise control over surface proximity and etching profile even at scaled-down dimensions where conventional control methods fail.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides improved control over the etching profile, resulting in increased saturation current, reduced short channel effects, and enhanced on/off speed of integrated circuit devices, while maintaining precise control over the source and drain regions.
Implementation Method 1
A method involving the formation of doped features in the source and drain regions with specific implantation processes
Implementation Method 2
followed by epitaxial growth of silicon or silicon germanium to create strained source and drain features
Data Source
AI summary
An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of an integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite to the LDD region.