Strained Source Drain Features in Integrated Circuit Devices
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Solution Overview
Problem
Existing semiconductor integrated circuit (IC) manufacturing techniques face challenges in achieving optimal transistor performance due to limitations in source and drain feature configurations and materials, particularly in scaling down processes where conventional approaches fail to adequately enhance carrier mobility and control short channel effects.
Innovation Solution
A method involving a semiconductor substrate with specific doping and epitaxial growth of different semiconductor materials in recesses formed on either side of gate structures to create strained source and drain features, enhancing carrier mobility and device performance by precise control over etching profiles and material selection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional epitaxial growth is used to form source and drain features, then manufacturing simplicity is maintained, but carrier mobility enhancement and short channel effect control are insufficient
Solution Approach 1:
The source and drain regions are segmented into multiple zones with different doping concentrations and material compositions. The method forms lightly doped source/drain regions with different doping profiles in different zones, allowing carrier mobility enhancement in channel-proximal zones while maintaining manufacturability through systematic segmentation of the epitaxial growth process into multiple controlled stages.
Solution Approach 2:
Different zones of the source and drain regions are assigned different local qualities through selective doping and material composition. The method implements different doping concentrations, epitaxial growth conditions, and material compositions (such as SiGe vs. Si) in different spatial zones, enabling localized carrier mobility enhancement and short channel effect control without compromising overall device manufacturability.
2Productivity
If geometry size is scaled down to increase functional density, then production efficiency and cost reduction are achieved, but processing complexity and difficulty in achieving optimal transistor performance increase
Solution Approach 1:
The method performs preliminary actions by forming offset spacers and defining etch stop layers before the main epitaxial growth process. These preliminary structures are prepared in advance to control the subsequent formation of source and drain features, enabling precise geometric control at scaled dimensions while maintaining production efficiency through pre-planned process sequencing.
Solution Approach 2:
Offset spacers and etch stop layers serve as intermediary structures that mediate between the lithography-defined gate patterns and the final source/drain feature geometry. These intermediary elements enable precise control of feature dimensions and doping profiles during scaling, bridging the gap between conventional manufacturing capabilities and advanced device geometry requirements.
3Reliability
If uniform doping is applied to source and drain regions, then manufacturing simplicity is maintained, but carrier mobility enhancement and saturation current control are limited
Solution Approach 1:
The doping process is transformed from uniform to locally differentiated by implementing multiple implantation steps with different dopant types, concentrations, and activation energies tailored to specific zones. Lightly doped zones near the channel receive different doping treatment than distal zones, creating local quality variations that enhance carrier mobility where needed while maintaining ease of manufacture through systematic process design.
Solution Approach 2:
The method systematically changes doping parameters including dopant concentration, implantation energy, and activation temperature across different zones and process steps. By varying these parameters in a controlled manner, the invention achieves superior carrier mobility and saturation current characteristics without excessive manufacturing complexity, as each parameter change serves a specific functional purpose in the device performance optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves carrier mobility, reduces short channel effects, and increases saturation current while maintaining control over source and drain feature dimensions, leading to enhanced IC device performance and efficiency.
Implementation Method 1
performing a first implantation process with a first dopant on the substrate, thereby forming a lightly doped source and drain (LDD) region
Implementation Method 2
epitaxially (epi) growing a first semiconductor material to fill the first recess; epitaxially (epi) growing a second semiconductor material to fill the second recess
Data Source
AI summary
An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.