Strained Source and Drain Structure for MOSFET Integration
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Solution Overview
Problem
Existing semiconductor device fabrication techniques for MOSFETs with stressor regions, such as epitaxially grown semiconductor materials for source and drain features, have limitations in achieving optimal transistor performance due to constraints in feature size and integration density, particularly in reducing the surface proximity between gate spacers and recesses, which affects carrier mobility and device performance.
Innovation Solution
The method involves forming doped regions in the substrate, controlling the surface proximity through precise etching processes, and depositing strained source and drain structures with a small surface proximity to the gate spacers, achieved by a combination of dry and wet etching techniques, allowing for reduced channel length and enhanced device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional epitaxial growth techniques are used to form source and drain features, then manufacturing process simplicity is maintained, but integration density and carrier mobility are insufficient
Solution Approach 1:
The source and drain formation process is segmented into multiple distinct steps: forming recesses in the substrate, depositing strained semiconductor material in the recesses, and performing selective doping. This segmentation allows each step to be optimized independently, achieving high integration density through precise control of surface proximity while managing fabrication complexity through systematic process breakdown.
Solution Approach 2:
Different regions of the substrate receive different treatments: recesses are formed in specific locations adjacent to gate spacers, strained semiconductor material is deposited only in these recesses, and doping is performed selectively. This local quality approach enables enhanced carrier mobility in critical regions (where strained material is present) while maintaining standard structure in other areas, thereby improving integration density without requiring complete process overhaul.
2Reliability
If surface proximity between gate spacers and recesses is reduced to enhance carrier mobility, then transistor performance improves, but manufacturing precision requirements increase
Solution Approach 1:
Recesses are formed in the substrate before depositing the strained semiconductor material, and the doping process is performed after material deposition. This preliminary action sequence allows precise control of surface proximity dimensions to be established early in the process, enabling subsequent steps to build upon these predetermined geometries without compromising manufacturing precision. The channel length is effectively reduced by controlling the distance between gate spacers and recess inner borders, enhancing carrier mobility while maintaining manufacturability.
Solution Approach 2:
The strained semiconductor material acts as an intermediary between the substrate recesses and the doped regions. By depositing this material layer within the recesses first, the process creates a defined intermediate structure that facilitates precise control of surface proximity. This intermediary layer enables the subsequent doping process to achieve the desired carrier concentration profiles while maintaining the geometric precision required for enhanced transistor performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves semiconductor device performance by reducing the channel length and enhancing carrier mobility, leading to better integration density and transistor efficiency.
Implementation Method 1
performing a dry etching process to remove a portion of the doped regions and to form a recess in the substrate
Implementation Method 2
performing a wet etching process to enlarge the recess to form an enlarged recess
Implementation Method 3
epitaxially grown semiconductor materials to form source and drain features
Implementation Method 4
Strained source and drain (SSD) structure... enhancing carrier mobility
Data Source
AI summary
Embodiments of mechanisms of forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on sidewalls of the gate stacks. The semiconductor device structure includes doped regions formed in the substrate. The semiconductor device structure also includes a strained source and drain (SSD) structure adjacent to the gate spacers, and the doped regions are adjacent to the SSD structure. The semiconductor device structure includes SSD structure has a tip which is closest to the doped region, and the tip is substantially aligned with an inner side of gate spacers.