Strained Source/Drain Extension Layer for MOSFET Dopant Control
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Solution Overview
Problem
The semiconductor industry faces challenges with increasing power consumption and short channel effects in metal oxide semiconductor field effect transistors due to excessive dopant diffusion and decreased drain current, especially as device dimensions shrink.
Innovation Solution
A method of fabricating metal oxide semiconductor field effect transistors involves forming strained source/drain extension and source/drain layers using selective epitaxial deposition, with a dopant diffusion barrier layer to control dopant diffusion and increase drain current, employing materials like silicon germanium and silicon carbide with gradient composition ratios to exert stress on the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dopant implantation is performed to improve short channel effect, then punch through is improved, but dopant diffusion rate is difficult to control and excessive dopant damages transistor efficiency
Solution Approach 1:
A barrier layer is introduced as an intermediary between the dopant source and the channel region. This barrier layer selectively blocks dopant diffusion into the channel while allowing controlled dopant presence in the source/drain extension, thereby resolving the contradiction between improving punch-through and controlling dopant diffusion precision.
Solution Approach 2:
The source/drain structure is segmented into distinct regions: a barrier layer, a source/drain extension layer with controlled dopant, and a lightly-doped drain region. This segmentation allows independent optimization of dopant distribution in each region, improving both punch-through and diffusion control.
2Reliability
If halo implant is used to inhibit punch through effect, then punch through is improved, but drain current decreases and transistor efficiency cannot further improve
Solution Approach 1:
The invention applies different doping concentrations and barrier properties to different spatial locations: a barrier layer at the channel interface to prevent punch-through, and a lightly-doped extension region that maintains drain current. This local differentiation resolves the contradiction between reliability and productivity.
Solution Approach 2:
The dopant concentration profile is changed from a conventional high-concentration halo implant to a gradient profile with a barrier layer (zero dopant concentration) adjacent to the channel, followed by a lightly-doped extension region. This parameter change improves punch-through while preserving drain current.
3Area of stationary object
If device dimensions are shrunk to increase integration density, then footprint area is reduced, but short channel effect becomes more pronounced and power consumption increases
Solution Approach 1:
A barrier layer is preliminarily positioned at the channel interface before dopant implantation. This preliminary action prevents the short channel effect from developing by blocking dopant diffusion into the channel, enabling further device scaling without sacrificing reliability.
Solution Approach 2:
The barrier layer acts as an intermediary structure that decouples the scaling benefits from the short channel effect penalties, allowing device dimensions to be reduced while maintaining electrical performance through controlled dopant distribution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively controls dopant diffusion, enhances transistor efficiency by increasing saturation and linear-region drain currents, and improves manufacturing reliability by managing dopant distribution.
Implementation Method 1
The source/drain extension layer and the source/drain layer are both strained layers
Implementation Method 2
the dopant diffusion rate is difficult to control, and excessive dopant will damage the transistor efficiency
Implementation Method 3
the structure of the aforementioned source/drain extension layer is, for example, epitaxy, and the method of fabrication of the source/drain extension layer is, for example, selective epitaxial deposition
Data Source
AI summary
A method of fabrication of a metal oxide semiconductor field effect transistor is disclosed. At first, a substrate on which a gate structure is formed is provided. Afterward, a portion of the substrate is removed to form a first recess in the substrate at both ends of the gate structure. Additionally, a source/drain extension layer is deposited in the first recess and a plurality of spacers are formed at both ends of the gate structure. Subsequently, a portion of the source/drain extension and the substrate are removed to form a second recess in the source/drain extension and a portion of the substrate outside of the spacer. In addition, a source/drain layer is deposited in the second recess. Because the source/drain extension and the source/drain layer have specific materials and structures, short channel effect is improved and the efficiency of the metal oxide semiconductor field effect transistor is improved.