Strained Substrate Integrated Circuit with Relaxed Buffer Layer
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Solution Overview
Problem
The use of tensile strained silicon-on-insulator substrates in semiconductor manufacturing renders conventional methods for adjusting the threshold voltage of PMOS transistors ineffective, as SiGe layers grown over tensile strained silicon form in a bi-axially expanded state, reducing compressive strain and limiting threshold voltage shifts, especially in high-k/metal gate stacks.
Innovation Solution
A method is developed to fabricate integrated circuits on strained substrates by embedding a relaxed buffer layer within a cavity etched into the substrate, allowing a body of strain material with an opposite strain orientation to be grown over the buffer layer, enabling compressively-strained materials to be introduced into PMOS channels, thereby optimizing carrier mobility and threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If compressive strain is applied to PMOS channel regions to adjust threshold voltage, then threshold voltage shifts are achieved, but the use of tensile strained substrates reduces the effectiveness of this strain application
Solution Approach 1:
A relaxed buffer layer is introduced as an intermediary between the tensile strained substrate and the compressively-strained SiGe layer. This buffer layer mediates the strain conflict by absorbing the lattice mismatch, allowing the SiGe layer to maintain its compressive strain state effectively for threshold voltage adjustment while the substrate maintains its tensile strain for NMOS performance.
Solution Approach 2:
A composite structure is formed consisting of multiple layers with different strain characteristics: the tensile strained silicon substrate, the relaxed buffer layer, and the compressively-strained SiGe layer. This composite material approach enables both tensile and compressive strain to coexist in the same device structure, achieving both carrier mobility enhancement and threshold voltage control.
2Temperature
If high-k/metal gate stacks are used in PMOS transistors, then thermal budget requirements are met, but significant threshold voltage shifts are required to enable metal usage
Solution Approach 1:
The relaxed buffer layer and compressively-strained SiGe layer are prepared in advance before the high-k/metal gate stack fabrication. This preliminary action ensures that the threshold voltage shift is already established by the strain structure, enabling the subsequent high-k/metal gate processing to proceed without requiring additional threshold voltage adjustment steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for significant threshold voltage shifts and improved carrier mobility in PMOS transistors, enabling the use of high-k/metal gate stacks by growing compressively-strained materials over relaxed buffer layers, while maintaining enhanced drive current and operational speed.
Implementation Method 1
the SiGe layer will form in a bi-axially expanded state to accommodate the larger lattice constant of the tensile strained silicon
Implementation Method 2
embedding a relaxed buffer layer within the cavity, forming a body of strain material over the relaxed buffer layer
Implementation Method 3
The mobility of holes, the majority carrier in a P-channel MOS (PMOS) transistor, can be enhanced by applying compressive stress to, and thereby inducing compressive strain within, the silicon of the PMOS channel region
Implementation Method 4
The gain of a MOS transistor, usually defined by the transconductance (gm), is proportional to the mobility (μ) of the majority carrier in the transistor channel
Implementation Method 5
the mobility of electrons, the majority carrier in an N-channel MOS (NMOS) transistor, can be increased by applying tensile stress to, and thereby inducing a tensile strain within, the silicon of the NMOS channel region
Data Source
AI summary
Embodiments of a method for producing an integrated circuit are provided, as are embodiments of an integrated circuit. In one embodiment, the method includes providing a strained substrate having an n-active region and a p-active region, etching a cavity into one of the n-active region and the p-active region, embedding a relaxed buffer layer within the cavity, forming a body of strain material over the relaxed buffer layer having a strain orientation opposite that of the strained substrate, and fabricating n-type and t-type transistors over the n-active and p-active regions, respectively. The channel of the n-type transistor extends within one of the strained substrate and the body of strain material, while the channel of the p-type transistor extends within the other of the strained substrate and the body of strain material.