Strained Transistor Formation via Late Amorphization and Disposable Spacers
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Solution Overview
Problem
The challenge in integrated circuit fabrication is to enhance charge carrier mobility in transistor channel regions while minimizing process complexity and production costs, as existing methods for creating strained channels often result in increased complexity and potential for reduced performance due to leakage currents and crystalline defects.
Innovation Solution
A technique involving the formation of a substantially amorphized region in a semiconductor layer, followed by re-crystallization under a stressed layer, with a reduced-width spacer for silicidation, and advanced anneal techniques to enhance strain induction and reduce defect formation, allowing for improved charge carrier mobility and conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If strained silicon layers are formed using conventional epitaxial growth techniques, then charge carrier mobility is enhanced, but manufacturing cost and process complexity increase significantly
Solution Approach 1:
The patent changes the fundamental approach from epitaxial growth to ion implantation followed by thermal annealing. This parameter change in the manufacturing process achieves strain induction without requiring complex epitaxial equipment or multi-step growth processes, thereby reducing process complexity while maintaining the ability to enhance charge carrier mobility through strain engineering
Solution Approach 2:
The patent replaces the chemical epitaxial growth process with a physical ion implantation process followed by thermal annealing. This substitution eliminates the need for sophisticated epitaxial reactors and complex in-situ growth control, simplifying the manufacturing system while achieving the same functional outcome of strain-induced mobility enhancement
2Speed
If channel length is reduced to increase operating speed, then conductivity improves, but leakage current increases and performance deteriorates
Solution Approach 1:
The patent applies strain locally to the channel region through targeted ion implantation and selective annealing processes. By creating localized strain in the channel area while maintaining the rest of the device structure unchanged, the patent enhances carrier mobility in the critical conduction path without affecting the overall device dimensions or introducing additional leakage paths that would result from further scaling
Solution Approach 2:
The patent performs strain induction through ion implantation and annealing before final device assembly and testing. This preliminary creation of strained regions ensures that the channel properties are optimized for high-speed operation with low leakage before the device is completed, allowing performance validation earlier in the manufacturing process
3Ease of manufacture
If amorphization is performed early in the process, then strain induction is facilitated, but crystalline defects increase and performance is reduced
Solution Approach 1:
The patent performs ion implantation to create amorphous regions as a preliminary step before applying the stressed spacer layer. This early amorphization facilitates subsequent strain transfer during the annealing process, as the amorphous material can more readily accommodate and transmit stress from the spacer layer without generating excessive crystalline defects
Solution Approach 2:
The patent optimizes the timing and parameters of the annealing process to transform the amorphous regions into strained crystalline structures. By carefully controlling the annealing temperature, duration, and atmosphere, the patent achieves complete recrystallization with minimal defect formation, converting the initially amorphous material into high-quality strained silicon that enhances carrier mobility without degrading device reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases charge carrier mobility, reduces series resistance, and minimizes leakage currents by efficiently generating strain in the channel region, thereby enhancing transistor performance without the need for expensive epitaxial growth techniques.
Implementation Method 1
a stressed layer having a specified intrinsic stress is formed at least above a portion of the semiconductor layer and the substantially amorphized region is re-crystallized in the presence of the stressed layer
Implementation Method 2
the substantially amorphized region is re-crystallized in the presence of the stressed layer by performing a heat treatment
Data Source
AI summary
By using a disposable spacer approach for forming drain and source regions prior to an amorphization process for re-crystallizing a semiconductor region in the presence of a stressed spacer layer, possibly in combination with enhanced anneal techniques, such as laser and flash anneal processes, a more efficient strain-generating mechanism may be provided. Furthermore, the spacer for forming the metal silicide may be provided with reduced width, thereby positioning the respective metal silicide regions more closely to the channel region. Consequently, an overall enhanced performance may be obtained on the basis of the above-described techniques.