Uniaxially Strained Transistor with Raised SiGe Source/Drain
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Solution Overview
Problem
State-of-the-art PMOSFETs with epitaxially grown SiGe channels face strain relaxation issues due to small active areas, leading to reduced stress on the channel and decreased device performance, as the embedded SiGe process fails to apply significant strain when the SiGe channel is already relaxed.
Innovation Solution
Fabricating PMOSFETs on long and narrow active regions with a raised SiGe source/drain structure instead of the conventional embedded SiGe process, employing faceted epitaxy to maintain uniaxial compressive strain and minimize parasitic capacitance, allowing multiple transistors to share a single active area and preserving strain in the channel direction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the embedded SiGe process is used to apply strain to the channel, then the parasitic resistance is reduced, but the strain is significantly relaxed when the SiGe channel is already relaxed, making the process ineffective
Solution Approach 1:
The patent applies preliminary action by forming the strained SiGe channel layer before creating the active region recesses. This ensures the channel is pre-strained before any relaxation can occur during subsequent processing steps, making the strain application effective even in narrow transistors where the channel length is small
Solution Approach 2:
The patent inverts the conventional sequence by forming the channel strain first, then creating the source/drain structures, rather than the traditional approach of forming source/drain regions first and then attempting to apply strain. This reversal ensures the channel maintains its strained state throughout the fabrication process
2Productivity
If the active area length is made small (typically 200 nm or less) for narrow transistors, then the transistor width can be reduced below 500 nm, but the biaxial compressive strain in the SiGe is almost completely relaxed
Solution Approach 1:
The patent applies local quality by creating a non-uniform active region geometry where the channel portion maintains the full strained SiGe layer thickness and strain, while the source/drain regions have recesses filled with differently strained SiGe. This local differentiation allows narrow transistors to maintain channel strain while achieving high density
Solution Approach 2:
The patent transitions from uniform biaxial strain in the planar direction to uniaxial strain by maintaining the full strained layer thickness in the channel region while creating depth variations in the source/drain regions. This dimensional approach preserves strain in the critical channel transport direction even when the active area is small
3Productivity
If faceted epitaxy is used to form raised source/drain regions, then parasitic capacitance is minimized and drive current is increased, but the fabrication process becomes more complex
Solution Approach 1:
The patent applies parameter changes by controlling the epitaxial growth conditions to form faceted raised source/drain regions with specific geometric characteristics. By adjusting growth parameters such as temperature, pressure, and gas flow rates, the faceted structure is formed that minimizes parasitic capacitance while maximizing drive current
Solution Approach 2:
The patent utilizes curved faceted surfaces in the raised source/drain regions formed through epitaxial growth. These curved geometries optimize the electric field distribution and minimize parasitic capacitance between the source/drain regions and the substrate, thereby improving drive current characteristics
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves high uniaxial compressive strain levels exceeding 2 GPa, independent of transistor pitch, significantly increasing drive current and hole mobility, making the technology scalable for future nodes while reducing contact resistance and parasitic capacitance.
Implementation Method 1
a strained semiconductor layer having a first strained axis
Implementation Method 2
significantly increasing drive current and hole mobility
Implementation Method 3
Epitaxially grown SiGe channels
Data Source
AI summary
A semiconductor device and method for fabricating a semiconductor device include providing a strained semiconductor layer having a first strained axis, forming an active region within a surface of the strained semiconductor layer where the active region has a longitudinal axis along the strained axis and forming gate structures over the active region. Raised source/drain regions are formed on the active regions above and over the surface of the strained semiconductor layer and adjacent to the gate structures to form transistor devices.