Strained Transistor Method with Selective Constraint Release
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Solution Overview
Problem
Current methods for producing microelectronic devices with constrained channel transistors are inefficient, as they apply a single constraint to all transistors, which can harm the operation of certain transistors, particularly PMOS transistors when a voltage constraint is applied, and require complex processes involving numerous steps of photolithography, etching, and epitaxy deposition.
Innovation Solution
A method involving the formation of a constraint layer on specific gate blocks and semiconductor zones, with a sacrificial layer between the constraint layer and certain transistors, allowing for the release of constraint on specific transistors by etching, enabling separate constraint application to different types of transistors while retaining the constraint layer for other functions like etching stop or insulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single constraint layer is applied to all transistors, then the manufacturing process is simplified, but the performance of certain transistors (e.g., PMOS) is harmed due to inappropriate constraint
Solution Approach 1:
The constraint layer application is segmented by transistor type through the use of sacrificial layers. NMOS transistors have sacrificial layers removed to allow constraint layer contact and compression constraint, while PMOS transistors retain sacrificial layers to prevent constraint layer contact and avoid voltage constraint. This segmentation enables differential constraint application based on transistor type requirements.
Solution Approach 2:
Different constraint conditions are applied locally to different transistor regions. The constraint layer is selectively positioned to contact only NMOS transistor regions (through sacrificial layer removal), while PMOS transistor regions maintain isolation. This local quality differentiation ensures each transistor type receives the appropriate constraint for optimal performance.
2Reliability
If multiple layers are used to constrain different transistor types separately, then transistor-specific performance is optimized, but the manufacturing process complexity increases
Solution Approach 1:
A single constraint layer structure serves multiple functions: it provides compression constraint to NMOS transistors where sacrificial layers are removed, and simultaneously acts as an etching stop layer and insulation layer for PMOS transistors where sacrificial layers are retained. This multi-functionality eliminates the need for separate constraint layers for different transistor types, simplifying the overall manufacturing process while maintaining transistor-specific performance optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the precise constraint of specific transistors while avoiding constraint on others, improving performance by allowing silicidation without limiting the channel zone of certain transistors, and shifting thermal budgets to the contact formation stage, thus enhancing the operational efficiency of microelectronic devices.
Implementation Method 1
Applying a constraint makes it possible to distort the crystal lattice of the semiconductor material and to modify its band structure and in particular the charge transport properties
Implementation Method 2
removing the sacrificial layer by etching through said openings
Data Source
Figure 1A~1C
Figure 2A~2B
Figure 2C~2D
AI summary
The present application relates to a method for making a microelectronic transistor device in which a stress layer is formed on a set of transistors and the stress exerted on at least one given transistor of this set is released by removing a sacrificial layer located between said given transistor and said stress layer.