Strained Transistor Silicidation via Selective Barrier Layers
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Solution Overview
Problem
Existing methods for manufacturing strained channel transistors, particularly for PMOS and NMOS types, face challenges in applying differential strain effectively, as external strain layers can harm some transistors, and require complex photolithography and etching steps.
Innovation Solution
A method involving the formation of a barrier layer on semiconducting zones, followed by metal deposition and annealing to create metal-semiconductor alloy zones that apply compressive strain, while maintaining strain through a dielectric barrier layer, allowing for differential strain application on transistors without reacting with the semiconductor material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an external strain layer is deposited on source and drain zones and gate to apply strain on transistor channels, then charge carrier mobility is improved, but the strain is applied indifferently on all transistors which can be harmful to operation of some transistors
Solution Approach 1:
The patent applies local quality by making the strain-inducing layer (silicon nitride) selective to specific transistor types through targeted deposition. The barrier layer configuration enables tensile strain to be applied only to PMOS transistors while NMOS transistors remain unaffected, allowing differential strain treatment based on local transistor type requirements.
Solution Approach 2:
The patent segments the strain application by dividing the device into regions with different barrier layer configurations. PMOS regions have barrier layers that allow silicon nitride deposition and strain application, while NMOS regions have barrier layers that prevent silicon nitride deposition, thus segmenting the strain effect by transistor type.
2Reliability
If a first layer of silicon nitride is deposited to apply tensile strain on all transistors, then tensile strained transistors are formed, but complex photolithography and etching steps are required to remove the layer from transistors that should not be strained
Solution Approach 1:
The patent applies preliminary action by configuring the barrier layers before silicon nitride deposition in such a way that selectively prevents deposition on NMOS regions. This preliminary configuration eliminates the need for subsequent complex photolithography and etching steps to remove strain layers from inappropriate transistor types.
Solution Approach 2:
The barrier layer acts as an intermediary that controls the interaction between the silicon nitride strain layer and the transistor regions. By having different barrier layer configurations on PMOS and NMOS regions, the intermediary selectively allows or prevents strain layer formation, simplifying the overall manufacturing process.
3Reliability
If metal is deposited and annealed to form metal-semiconductor alloy zones for compressive strain, then compressively strained PMOS transistors are formed, but the metal may react with or diffuse into the semiconductor material
Solution Approach 1:
The barrier layer serves as an intermediary between the metal and the semiconductor material during the silicidation process. It allows the metal to react with and diffuse into the semiconductor to form the desired metal-semiconductor alloy zones for compressive strain, while simultaneously preventing excessive reaction and diffusion that would harm the transistor operation.
Solution Approach 2:
The patent applies parameter changes by precisely controlling the annealing conditions (temperature, time, atmosphere) of the metal deposition process. These parameter changes enable the formation of metal-semiconductor alloy zones with the desired strain effect while limiting harmful reactions and diffusion through optimized process parameters.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the production of transistors with controlled compressive or tensile strain, improving charge carrier mobility and reducing the complexity of manufacturing by avoiding strain-induced damage and simplifying the process through silicidation and barrier layer confinement.
Implementation Method 1
deposit a metallic material, followed by annealing, so as to form metal and semiconductor alloy zones
Implementation Method 2
the volume of metallic material deposited on the first semiconducting zones and the annealing duration being chosen so as to form first metal and semiconductor alloy zones applying a compressive strain on a channel zone
Implementation Method 3
formation of a barrier layer on semiconducting zones... a barrier layer based on a given material on first semiconducting zones... different from the material used in said first semiconducting zones
Data Source
AI summary
A method for making a microelectronic device with transistors, in which silicided source and drain zones are formed to apply a compressive strain on the channel, in some transistors.