Strained Transistor With Sloped Gate Sidewalls
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Solution Overview
Problem
As transistors shrink in size, they experience increased interference from adjacent electric fields and leakage currents, leading to performance degradation and power inefficiency, which becomes more challenging to address beyond the 32 nm and 16 nm nodes in CMOS technology.
Innovation Solution
The formation of a transistor with sloped sidewalls and a strain-inducing silicon nitride layer that induces compressive or tensile stress, allowing for enhanced carrier mobility and reduced power dissipation by customizing dopant concentration gradients and using a conformal strain-inducing layer to improve channel region conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor size is reduced to increase circuit density, then more transistors can be placed in a smaller area, but leakage currents increase and performance degrades
Solution Approach 1:
The patent applies local quality by creating asymmetric dopant concentration distributions within the channel region. By implanting dopants at different doses and angles to create distinct concentration zones (higher near source/drain, lower in center), the channel exhibits different electrical properties in different regions, optimizing both current drive and leakage control locally throughout the channel structure.
Solution Approach 2:
The patent changes physical parameters by varying dopant concentration, implantation angle, and energy to create a non-uniform dopant profile. This parameter variation throughout the channel region modifies the electrical characteristics, enabling improved carrier mobility and reduced off-state leakage currents simultaneously.
2Speed
If transistor size is reduced to improve switching speed, then switching speed increases, but electric field interference between adjacent transistors increases
Solution Approach 1:
The patent creates localized electrical field control through asymmetric dopant distribution. The varying dopant concentration zones modify the electric field profile within the channel, confining and controlling electric fields to reduce their reach and interference with adjacent transistors while maintaining high switching speed in the optimized channel region.
3Ease of manufacture
If conventional vertical gate sidewalls are used, then manufacturing is simpler, but strain induction efficiency is reduced
Solution Approach 1:
The patent employs asymmetry by creating non-uniform dopant concentration distributions within the channel rather than symmetric uniform doping. This asymmetric doping profile, combined with the strain inducing layer, creates optimized electrical fields and strain distributions that enhance carrier mobility while maintaining manufacturability through standard implantation techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances transistor performance by increasing carrier mobility, reducing power consumption, and enabling lower supply voltages, while maintaining efficient channel length and minimizing parasitic effects, thus improving overall integrated circuit performance.
Implementation Method 1
A strain inducing layer is formed over the gate electrode conformal with the surface of the gate electrode. The strain inducing layer induces strain in the channel region of the transistor.
Implementation Method 2
The strain inducing layer induces strain in the channel region of the transistor. The improved carrier mobility enhances current conduction in the channel region
Data Source
AI summary
A strain enhanced transistor is provided having a strain inducing layer overlying a gate electrode. The gate electrode has sloped sidewalls over the channel region of the transistor.