Strained Transistor Stressor Layer and Trench Isolation
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Solution Overview
Problem
Existing methods for forming strained transistors face challenges in precisely applying stress to the channel region and require complex process steps, leading to inefficiencies and defects such as stress risers in trench isolation regions.
Innovation Solution
A strain-inducing layer, such as silicon nitride or silicon dioxide, is deposited over transistors and within trench isolation regions, providing compressive or tensile stress to enhance carrier mobility, while a low-k dielectric material improves insulation and allows for narrower trench isolation, reducing capacitive coupling and stress risers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dielectric layer is deposited overlying the transistor structure to induce stress, then carrier mobility is improved, but the stress is only indirectly applied to the channel region and difficult to precisely apply
Solution Approach 1:
The patent introduces a stressor layer as an intermediary element that directly contacts the channel region through the gate dielectric interface. This stressor layer, deposited conformally over the gate electrode and sidewall spacers, serves as a mediator to transmit stress directly to the channel region rather than indirectly through the entire transistor structure, thereby achieving precise stress application.
Solution Approach 2:
The stressor layer is positioned locally over the gate electrode and sidewall spacers, creating a localized stress field precisely where needed in the channel region. This localized stress application enhances carrier mobility in the specific area of the channel beneath the gate, while avoiding unnecessary stress in other regions of the transistor structure.
2Reliability
If conventional trench isolation regions are used between adjacent transistors, then electrical isolation is provided, but stress risers are created in the trench isolation regions
Solution Approach 1:
The patent modifies the physical and material parameters of the trench isolation region by filling it with a dielectric material that has different mechanical properties than the surrounding structures. This change in material parameters reduces the stress concentration effects at the trench corners while maintaining the electrical isolation function, thereby eliminating stress risers without compromising isolation performance.
3Object-affected harmful factors
If wider trench isolation regions are used to reduce stress risers, then fewer defects are created, but capacitive coupling between adjacent transistors increases
Solution Approach 1:
The patent employs a composite structure in the trench isolation region by filling it with a dielectric material that combines electrical isolation properties with reduced mechanical stress effects. This composite approach allows the trench isolation to simultaneously prevent defects from stress risers and minimize capacitive coupling, achieving both goals with an optimized material composition rather than increasing the physical width.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively increases carrier mobility, enhances transistor performance, and minimizes defects by directly applying stress to the channel region and improving insulation between transistors, leading to improved strained transistor structures with reduced capacitive coupling and defects.
Implementation Method 1
a transistor subjected to different types of stress increases the mobility of the charge carriers in the channel region. For example, creating a tensile stress in the channel region increases the mobility of electrons
Implementation Method 2
A dielectric layer 9, which is compressively stressed, is then deposited overlying the semiconductor integrated circuit structure
Data Source
AI summary
According to one embodiment, a semiconductor substrate is provided having at least two transistor regions formed therein. Overlying the channel regions is a gate dielectric and transistor gate electrodes overly the gate dielectric and are positioned overlying the channel regions. Source and drain regions are formed on either side of the channel regions to create a transistor structure. In order to provide isolation between transistors in the semiconductor substrate, a trench is formed in the substrate. A strain-inducting layer is then deposited over the transistor structures and into the trench in the semiconductor substrate. A high-stress nitride layer is one type of material which is suitable for forming the strain-inducing layer.