Strained Tunable Nanowire Structures and Isolated Process Flow
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Solution Overview
Problem
Existing fabrication techniques for NMOS and PMOS nanowire transistors are limited by inherent coupling between NMOS and PMOS nanowire geometries and characteristics, making it difficult to independently tune performance parameters such as short channel effects, gate drive, and strain, which hinders device efficiency and performance.
Innovation Solution
The development of an isolated process flow (IPF) and deep-well process flow (DWPF) allows for independent tuning of NMOS and PMOS nanowire geometries, chemical composition, and other attributes, decoupling their fabrication to enable independent control of performance characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If top down fabrication process with alternating NMOS and PMOS material layers is used, then both NMOS and PMOS nanowires can be formed in the same process, but the geometries of NMOS and PMOS nanowires are inherently coupled and cannot be tuned independently
Solution Approach 1:
The fabrication process is segmented into separate isolated process flows for NMOS nanowires and PMOS nanowires. Instead of forming both types of nanowires simultaneously in a single alternating layer structure, the patent divides the fabrication into distinct process sequences that can be executed independently, allowing each nanowire type to be optimized without geometric constraints from the other.
Solution Approach 2:
The patent extracts the coupling constraint by removing the requirement for alternating NMOS and PMOS material layers. Each nanowire type is fabricated separately without the other present in the structure, thereby taking out the inherent geometric coupling that prevented independent tuning of Short Channel Effects, gate drive, and strain characteristics.
2Productivity
If transistor size is reduced to increase density, then more transistors can be packed per unit area, but Short Channel Effects and intrinsic device performance barriers worsen
Solution Approach 1:
The patent transitions from planar 2D transistor designs to three-dimensional vertically stacked nanowire structures. By stacking multiple nanowires vertically, the design achieves higher transistor density without further reducing the lateral dimensions of individual transistors, thereby maintaining acceptable Short Channel Effects while increasing productivity.
Solution Approach 2:
The patent applies local quality by enabling independent optimization of each nanowire's geometric and material properties. Each nanowire can be tailored with specific dimensions, strain characteristics, and material composition to optimize device performance, allowing high density through stacking while maintaining reliability through localized quality control.
3Reliability
If strained nanowires are used to improve carrier mobility, then device performance improves, but the fabrication process becomes more complex
Solution Approach 1:
The patent employs parameter changes by systematically varying material composition ratios, layer thicknesses, and strain levels in the nanowire structures. By independently controlling these parameters in isolated fabrication processes, the patent achieves optimized carrier mobility through strain engineering without excessive complexity, as each parameter can be adjusted separately rather than in coupled alternating structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables independent tuning of NMOS and PMOS nanowire transistors, reducing short channel effects, improving carrier mobility, and optimizing transistor performance by allowing for distinct geometrical and compositional variations, thereby enhancing device efficiency and flexibility.
Implementation Method 1
at least one strained n-type nanowire above the buffer layer, at least one strained p-type nanowire above the buffer layer
Data Source
AI summary
Fabrication techniques for NMOS and PMOS nanowires leveraging an isolated process flow for NMOS and PMOS nanowires facilitates independent (decoupled) tuning/variation of the respective geometries (i.e., sizing) and chemical composition of NMOS and PMOS nanowires existing in the same process. These independently tunable degrees of freedom are achieved due to fabrication techniques disclosed herein, which enable the ability to individually adjust the width of NMOS and PMOS nanowires as well as the general composition of the material forming these nanowires independently of one another. In the context of nanowire based semiconductors, in which NMOS and PMOS nanowires are incorporated as channel, drain and source regions respectively for NMOS and PMOS nanowire transistors, independent tuning of the NMOS and PMOS nanowires facilitates independent tuning of short-channel effects, gate drive, the width of the transistor dead space capacitance, strain and other performance related characteristics of associated NMOS and PMOS nanowire transistors.