Strained Vertical Channel Structure for Precise Gate and Thickness Control
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing integration density and enhancing performance due to limitations in device structure, particularly in controlling the thickness or diameter of vertical nanosheets or nanowires and introducing stress to improve device performance.
Innovation Solution
A semiconductor device with a strained vertical channel portion is developed, featuring source/drain portions at the ends of a vertically oriented channel layer, surrounded by gate stacks on opposite sides, where the gate dielectric layers partially overlap, and the channel layer is formed through epitaxial growth to introduce strain and improve morphology and dimension control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional vertical nanosheet or nanowire devices are used, then device structure is simple, but it is difficult to control the thickness or diameter of the nanosheets or nanowires
Solution Approach 1:
The gate structure is divided into two separate gate stacks (first gate stack and second gate stack) positioned on opposite sides of the vertical channel. Each gate stack independently controls one side of the channel, enabling precise control of channel thickness through the spacing between the two gates while maintaining a relatively simple overall device architecture.
Solution Approach 2:
The patent changes the gate structure from a single gate to dual gates with partial overlap of gate dielectric layers. This parameter change enables independent adjustment of gate voltages and precise control of channel dimensions, achieving better thickness control without significantly complicating the device structure.
2Reliability
If traditional vertical devices are used, then device structure is simple, but it is difficult to introduce stress to improve device performance
Solution Approach 1:
The patent introduces strain into the vertical channel portion through the dual gate structure with overlapping dielectric layers. The localized stress/strain is applied precisely where needed in the channel region to enhance carrier mobility and device performance, while the rest of the device structure remains relatively simple and unchanged.
Solution Approach 2:
The patent modifies the gate structure parameters by adding a second gate stack with partial overlap of dielectric layers, enabling stress engineering in the vertical channel. This parameter change allows introduction of beneficial stress to improve device performance without requiring complete restructuring of the device.
3Productivity
If integration density is increased, then device performance should improve, but traditional structures cannot meet the requirements
Solution Approach 1:
The patent transitions from planar gate control to three-dimensional vertical channel control with dual gates positioned on opposite sides. This dimensional change allows independent control of channel dimensions in multiple directions, enabling precise thickness control while achieving higher integration density through the vertical architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design allows for better control of channel thickness and gate length, enhancing device performance by introducing strain in the channel layer, which improves integration density and performance beyond traditional methods.
Implementation Method 1
the channel layer is formed through epitaxial growth to introduce strain and improve morphology and dimension control
Data Source
AI summary
A strained vertical channel semiconductor device, a method of manufacturing the same, and an electronic apparatus including the same are provided. The method includes: providing a vertical channel layer on a substrate, wherein the vertical channel layer is held by a first supporting layer on a first side in a lateral direction, and is held by a second supporting layer on a second side opposite to the first side; replacing the first supporting layer with a first gate stack while the vertical channel layer is held by the second supporting layer; and replacing the second supporting layer with a second gate stack while the vertical channel layer is held by the first gate stack.