Strained Vertical FinFETs via Bottom Condensation
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Solution Overview
Problem
Current methods for fabricating vertical fin field effect transistors (FinFETs) face challenges in scaling down device components, particularly in inducing compressive stress in the channel region to enhance performance, which is crucial for maintaining transistor efficiency as device dimensions decrease.
Innovation Solution
The method involves forming a counter-doped layer on a substrate, followed by creating a silicon-germanium source/drain layer and forming vertical fins. By oxidizing the exposed portions of the source/drain regions, a condensation process is used to increase the germanium concentration, creating a compressive strain in the vertical fin channel through lattice modification, thereby anchoring the fin and inducing compressive stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device dimensions are decreased to improve integration density, then productivity increases, but manufacturing precision deteriorates due to difficulty in forming individual components and electrical contacts
Solution Approach 1:
The patent transitions from planar FET structures to vertical FinFET structures, moving the channel formation into the third dimension. The fin extends vertically from the substrate surface, allowing current to flow through a three-dimensional path rather than a two-dimensional plane. This dimensional change enables higher integration density while maintaining manufacturable component sizes, as the vertical fin structure can be formed using standard epitaxial growth processes followed by selective removal of sacrificial layers.
2Ease of manufacture
If traditional FET structures are used to maintain ease of manufacture, then manufacturing precision is preserved, but device dimensions cannot be scaled down effectively
Solution Approach 1:
The patent segments the source/drain structure into multiple components: a bottom source/drain region formed in the substrate, vertical fins extending upward, and top source/drain regions. Sacrificial layers are used to define and separate these components during fabrication. This segmentation allows each component to be formed using established processes while achieving scaled-down device dimensions through the vertical fin architecture.
3Manufacturing precision
If compressive stress is not induced in the channel, then manufacturing precision is maintained, but transistor performance deteriorates at scaled dimensions
Solution Approach 1:
The patent changes the material composition parameter of the source/drain regions by forming silicon-germanium alloys with varying germanium concentrations. The germanium content is specifically controlled to induce compressive stress in the silicon channel when the source/drain layers are formed. This parameter change allows simultaneous achievement of manufacturing precision through standard epitaxial processes and enhanced transistor performance through stress-induced carrier mobility improvement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively enhances the performance of vertical FinFETs by introducing compressive strain in the channel, improving the transistor's efficiency and scalability, making it suitable for applications in CMOS devices and other logic and memory devices.
Implementation Method 1
oxidizing an exposed portion of each of the one or more bottom source/drain regions with a reactant to form a disposable layer
Implementation Method 2
a condensation process is used to increase the germanium concentration, creating a compressive strain in the vertical fin channel through lattice modification
Data Source
AI summary
A method of forming a strained vertical p-type field effect transistor, including forming a counter-doped layer at a surface of a substrate, forming a source/drain layer on the counter-doped layer, forming one or more vertical fins on the source/drain layer, removing a portion of the source/drain layer to form one or more bottom source/drains below each of the one or more vertical fins, reacting an exposed portion of each of the one or more bottom source/drains with a reactant to form a disposable layer on opposite sides of each bottom source/drain and a condensation layer between the two adjacent disposable layers, and removing the disposable layers.