Poly-Stranded FEC Layout for Parallel Optical Error Correction

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Solution Overview

Problem

Conventional forward error correction techniques in optical communication systems, such as product codes and braided codes, have inferior error rates and are not amenable to efficient parallel implementation, which is crucial for high-speed communication systems.

Innovation Solution

The development of poly-stranded error correcting codes, which organize data bits into a specific arrangement of blocks and columns, allowing for parallel encoding and decoding using multiple strands, and employing different error correcting codes in each strand to generate parity bits, facilitating high-speed and reliable data transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional forward error correction techniques (product codes, braided codes) are used, then implementation is simpler, but error rates are inferior and parallel processing capability is limited

Engineering Contradiction:
Improveerror rateVSAvoidcoding structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the data into multiple strands, where each strand is independently encoded using a base error correcting code. This segmentation enables parallel processing of multiple strands simultaneously, improving both error correction capability and processing efficiency. The overall code is constructed by combining these independently encoded strands, achieving superior error rates while maintaining parallel implementation capability.

Inventive Principle:
Principle #1Segmentation

2Productivity

If conventional FEC codes are used, then coding structure is simpler, but parallel encoding and decoding efficiency is reduced

Engineering Contradiction:
Improveparallel processing efficiencyVSAvoidcode structure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The data is divided into multiple independent strands that can be encoded and decoded in parallel. Each strand undergoes independent error correction coding, allowing simultaneous processing without inter-dependencies, thereby significantly improving parallel processing efficiency and throughput.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs a universal base error correcting code that can be applied to multiple strands in the same manner. This universal coding approach simplifies the overall system architecture while enabling efficient parallel processing, as the same encoding/decoding machinery can be replicated and applied to each strand independently.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If higher redundancy is added to improve error correction, then error rates decrease, but transmission overhead increases

Engineering Contradiction:
Improveerror correction capabilityVSAvoidtransmission overhead
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

By segmenting data into multiple strands and applying error correction to each strand independently, the patent achieves distributed redundancy. This approach improves error correction capability without concentrating all redundancy in a single overhead burden, as each strand carries its own localized redundancy that can be independently utilized.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10440759B1Forward error correction systems and methods
Publication Date: 2019.10.08 ACACIA TECH INC
  • US10440759B1 patent drawing
  • US10440759B1 patent drawing
  • US10440759B1 patent drawing

AI summary

Techniques for performing forward error correction of data to be transmitted over an optical communications channel. The techniques include: receiving data bits; organizing the data bits into an arrangement having a plurality of blocks organized into rows and columns and into a plurality of strands including a first strand of blocks that includes a back portion comprising a first row of the plurality of blocks, and a front portion comprising blocks from at least two different columns in at least two different rows other than the first row of blocks; and encoding at least some of the data bits in the arrangement using a first error correcting code at least in part by generating first parity bits by applying the first error correcting code to first data bits in the front portion of the first strands and second data bits in the back portion of the first strand.