Strap Cell Circuit for Memory Array Efficiency
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Solution Overview
Problem
In semiconductor memory devices, a large number of periodically recurring straps between memory arrays can negatively impact array efficiency due to increased area costs and issues such as read disturbance and dummy read disturbance during access operations.
Innovation Solution
The implementation of strap cell regions with circuits, including cross-coupled PMOS transistors and pass gates, which facilitate access operations and reduce the risk of read and dummy read disturbances by managing voltage levels between bit lines, thereby optimizing area usage and operational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a large number of periodically recurring straps are used to separate memory arrays, then the memory device can accommodate more memory arrays, but array efficiency deteriorates due to increased area cost and read disturbance
Solution Approach 1:
The patent extracts the strap cell region from the traditional separator structure and transforms it into an active functional unit with circuits. By taking out the strap's purely separative function and replacing it with circuitry that actively manages bit line voltages, the design eliminates read disturbance while maintaining array separation, thus resolving the contradiction between accommodating more arrays and maintaining efficiency
Solution Approach 2:
The strap cell region acts as an intermediary structure between adjacent memory arrays. Instead of being a passive barrier, it contains circuits that mediate the electrical interactions between bit lines of different arrays, preventing read disturbance by actively managing voltage levels and isolating signal paths while allowing necessary electrical connectivity
2Quantity of substance
If a large number of periodically recurring straps are used to separate memory arrays, then the memory device can accommodate more memory arrays, but area cost increases
Solution Approach 1:
The strap cell region is designed to perform multiple functions simultaneously: it separates adjacent memory arrays, provides active read disturbance prevention through voltage management circuits, and enables efficient bit line control. By making the strap region multi-functional rather than purely separative, the design eliminates the need for additional peripheral circuits, thereby reducing overall area cost while accommodating more arrays
3Device complexity
If traditional strap separation is used without active circuits, then the structure is simple, but read disturbance and dummy read disturbance occur during access operations
Solution Approach 1:
The circuits in the strap cell region perform preliminary actions by actively managing and stabilizing bit line voltage levels before and during memory array access operations. The voltage management circuits preemptively prevent read disturbance by ensuring proper voltage conditions are established in advance, eliminating the need for complex post-correction mechanisms and maintaining structural simplicity while improving reliability
Data Source
AI summary
A circuit comprises a first transistor and a second transistor in a strap cell region between a first memory array and a second memory array of a memory device. The first transistor includes a first node connected to a first data line, and a second node connected to a second data line. The first node and the second node of the first transistor are complementary to each other in voltage level. Further, the second transistor includes a first node connected to the second data line, and a second node connected to the first data line. The first node and the second node of the second transistor are complementary to each other in voltage level.