Strapped Copper Interconnect Layout for Electromigration Reliability
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Solution Overview
Problem
Current semiconductor devices with high current density interconnects are prone to electromigration damage, leading to increased resistance and potential failure, which is not effectively addressed by existing methods that often require significant modifications to process flows or result in reduced current-carrying capability.
Innovation Solution
The use of strapped interconnect lines with closely spaced vias that span the width of the lines, employing a tantalum liner to block copper diffusion along the interface with the dielectric cap, effectively limiting the diffusion path and enhancing electromigration reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wide interconnects are used to reduce current density, then electromigration reliability is improved, but die size increases
Solution Approach 1:
The interconnect structure is segmented into multiple copper layers (first copper layer and second copper layer) connected by strapping vias. This segmentation allows current to distribute across multiple paths, effectively reducing current density without requiring wider individual interconnect lines, thus maintaining small die size while improving electromigration reliability.
Solution Approach 2:
The solution transitions from a single-plane interconnect to a three-dimensional stacked structure with copper layers at different levels connected by vertical strapping vias. This dimensional change enables current to flow through multiple layers, reducing current density without increasing the planar footprint, thereby improving electromigration reliability without increasing die size.
2Area of stationary object
If higher current density is allowed, then die size is reduced, but electromigration damage increases
Solution Approach 1:
By dividing the current path into multiple copper layers connected by strapping vias, the total current is distributed across several segments. This allows higher overall current capacity within the same die area while maintaining lower current density in each individual segment, preventing electromigration damage.
Solution Approach 2:
The interconnect structure uses a composite arrangement of multiple copper layers with tantalum barrier layers and dielectric materials. This composite structure provides both high current-carrying capability and protection against electromigration, enabling high current density without compromising reliability.
3Duration of action of stationary object
If tantalum liner is added to block copper diffusion, then electromigration lifetime is improved, but device complexity increases
Solution Approach 1:
The tantalum liner acts as an intermediary barrier layer between the copper interconnect and the dielectric cap. It specifically blocks copper diffusion along the interface without interfering with the electrical function of the interconnect, thereby extending electromigration lifetime while adding minimal structural complexity.
Solution Approach 2:
The tantalum liner is applied locally only at critical interfaces where copper diffusion is most problematic (at the copper-dielectric cap interface), rather than throughout the entire device. This localized application effectively extends electromigration lifetime while minimizing the increase in device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases the electromigration lifetime of copper interconnects by up to five times, allowing for higher current-carrying capability without increasing die size, while maintaining low on-resistance and reducing copper diffusion, thus providing a robust alternative to conventional methods.
Implementation Method 1
employing a tantalum liner to block copper diffusion along the interface with the dielectric cap
Implementation Method 2
A plurality of strapping vias are connected between the first interconnect line and the second interconnect line
Data Source
AI summary
A semiconductor device a strapped interconnect line, which in turn includes a first interconnect line at a first level above a semiconductor substrate, and a second interconnect line at a second level above the interconnect substrate. A dielectric capping layer is located directly on the first interconnect line. A plurality of strapping vias are connected between the first interconnect line and the second interconnect line. Each of the strapping vias extends from a first side of the first interconnect line to a second side of the second interconnect line.