Strapped Dual-Gate VDMOS Reduces Gate-Drain Capacitance
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Solution Overview
Problem
Power VDMOS devices face limitations in reducing gate-to-drain capacitance, which restricts their operating frequency and efficiency in applications like buck converters due to high on-state resistance and parasitic capacitances.
Innovation Solution
The implementation of a strapped dual-gate configuration in VDMOS devices, featuring a semiconductor substrate with epitaxial and JFET diffusion regions, and a dual-gate structure with a conductive layer to reduce gate-to-drain capacitance and lower effective resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional single-gate VDMOS structure is used, then the device structure is simple, but the gate-to-drain capacitance is high which limits operating frequency
Solution Approach 1:
The gate is divided into two separate gate regions (first gate region and second gate region) that are spaced apart from each other. This segmentation reduces the overlap area between the gate and drain, thereby reducing the gate-to-drain capacitance and enabling higher operating frequencies while maintaining a relatively simple device structure.
2Speed
If the gate-to-drain capacitance is reduced by increasing gate spacing, then the operating frequency improves, but the effective gate resistance increases
Solution Approach 1:
A conductive layer is formed that electrically connects the first gate region and the second gate region. This merging of the two separated gate regions through a low-resistance conductive path reduces the effective gate resistance, compensating for the increased spacing between gates and enabling high-frequency operation with improved reliability.
3Loss of energy
If the drift region length is increased to reduce on-state resistance, then the conduction loss decreases, but the device area increases
Solution Approach 1:
The patent transitions from a conventional planar gate structure to a three-dimensional dual-gate configuration where gates are positioned at different vertical levels and spaced horizontally. This dimensional change allows for reduced gate-to-drain overlap capacitance without requiring increased drift region length, thereby reducing conduction loss without proportionally increasing device area.
Data Source
AI summary
Semiconductor devices are described that include a dual-gate configuration. In one or more implementations, the semiconductor devices include a substrate having a first surface and a second surface. The substrate includes a first and a second body region formed proximal to the first surface. Moreover, each body region includes a source region formed therein. The substrate further includes a drain region formed proximal to the second surface and an epitaxial region that is configured to function as a drift region between the drain region and the source regions. A dual-gate is formed over the first surface of the substrate. The dual-gate includes a first gate region and a second gate region that define a gap there between to reduce the gate to drain capacitance. A conductive layer may be formed over the first gate region and the second gate region to lower the effective resistance of the dual-gate.