Strapping Cells for Memory Array Uniformity
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Solution Overview
Problem
The operational and electrical characteristics of memory cells in semiconductor devices vary significantly depending on their location within the memory array due to differences in lithography density, well-proximity effects, and stress induced by shallow-trench isolations, leading to inconsistent performance across the chip.
Innovation Solution
The introduction of strapping cells between adjacent rows of memory cells, with conductive straps connecting N-type and P-type active areas, and the use of dummy wells along the edge to balance well proximity effects, along with conductive lines forming gate electrodes in series to enhance isolation and reduce stress-induced variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are arranged in a dense array to increase storage capacity, then productivity and quantity increase, but manufacturing precision and operational consistency deteriorate due to lithography density variations and well-proximity effects
Solution Approach 1:
Strapping cells are introduced as intermediary structures between adjacent rows of memory cells. These strapping cells contain active regions that are electrically connected to the active regions of neighboring memory cell rows through conductive straps, serving as a mediating element to balance well-proximity effects and distribute stress uniformly across the memory array, thereby improving operational consistency without reducing array density
Solution Approach 2:
The patent applies local modifications by selectively placing strapping cells at specific locations between memory cell rows and using dummy wells at array edges. These localized structures create non-uniform doping profiles and stress distributions that compensate for the non-uniformities caused by lithography density variations and edge effects, thereby improving overall manufacturing precision and cell characteristic consistency
2Area of stationary object
If shallow-trench isolations are used to increase device density, then area efficiency improves, but stress is induced in the channel region altering operational characteristics
Solution Approach 1:
The patent modifies the stress parameters in the channel region by introducing strapping cells with appropriately doped active regions. These strapping cells create compensating stress fields that counterbalance the stress induced by shallow-trench isolations, thereby altering the local stress parameters to achieve more uniform threshold voltages and on/off current levels across the memory array while maintaining high device density
Data Source
AI summary
A memory array with a row of strapping cells is provided. In accordance with embodiments of the present invention, strapping cells are positioned between two rows of a memory array. The strapping cells provide a P+ strap between N+ active areas of two memory cells in a column and provide an N+ strap between P+ active areas of two memory cells in a column of the memory array. The strapping cells provide an insulating structure between the two rows of the memory array and create a more uniform operation of the memory cells regardless of the positions of the memory cells within the memory array. In an embodiment, a dummy N-well may be formed along the outer edge of the memory array in a direction perpendicular to the row of strapping cells. Furthermore, transistors may be formed in the strapping cells to provide additional insulation between the strapped memory cells.