Strapping Lines Reduce SGD RC Delay in 3D NAND
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Solution Overview
Problem
Current 3D-NAND devices face challenges in reducing the RC delay of select-gate-for-drain (SGD) transistors due to high word line resistance, which affects the performance of memory cells, especially when using silicon-based word lines.
Innovation Solution
The implementation of strapping lines with lower resistance metal connections to SGD transistors, reducing RC delay by connecting SGD transistors to strapping lines in multiple positions, and optimizing the memory stack structure with alternating layers and selective etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If silicon-based word lines are used in 3D-NAND devices, then manufacturing is easier and device structure is simpler, but word line resistance increases causing higher RC delay
Solution Approach 1:
The patent introduces strapping lines as separate dedicated low-resistance connection paths that segment the electrical connection between SGD transistors and bit lines. Instead of relying solely on the word line for both selection and low-resistance connection, the strapping lines provide a parallel low-resistance path, effectively dividing the current flow to reduce overall resistance and RC delay while maintaining silicon-based word lines.
Solution Approach 2:
The patent introduces strapping lines as intermediary elements between the SGD transistors and the bit lines. These strapping lines act as mediators that provide a low-resistance electrical path, separating the function of word line selection from the function of low-resistance signal transmission, thereby reducing RC delay without changing the word line material.
2Area of stationary object
If the number of holes between slits (nHole) is increased to reduce array size, then device density improves, but more SGD cuts are needed increasing device complexity
Solution Approach 1:
The strapping lines serve multiple functions: they provide low-resistance electrical connections for signal transmission, act as structural support elements between memory holes, and enable independent selection of holes under the same bit line. This multi-functionality allows the patent to increase nHole for better density without proportionally increasing SGD cut complexity, as the strapping lines handle both electrical and structural roles.
Data Source
AI summary
Described is a semiconductor memory device and methods of manufacture. The semiconductor memory device comprises a memory array comprising at least one select-gate-for-drain (SGD) transistor and at least one memory transistor, the memory array having at least one strapping region and at least one strapping contact, the strapping contact connecting a select-gate-for-drain (SGD) transistor to a strapping line.