Stratified Underfill for Low-k IC Packages
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Solution Overview
Problem
The semiconductor industry faces challenges with thermal mismatch issues in flip chip packages due to the use of low-k dielectric materials and lead-free solder, leading to reliability problems such as solder bump cracking and underfill delamination, especially during temperature cycling tests.
Innovation Solution
A stratified underfill layer with varying coefficients of thermal expansion (CTE) is introduced between the integrated circuit die and the package substrate or printed circuit board, comprising multiple layers with different CTE values or filler concentrations, to mitigate thermal stresses and improve adhesion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low-k dielectric materials are used in interconnect layers, then resistance is reduced and reliability is improved, but thermal mismatch problem increases causing stress on low-k layers
Solution Approach 1:
The patent changes the CTE parameter of the underfill material to match the low-k dielectric layer (approximately 8 ppm/C) rather than using conventional high CTE materials (30-50 ppm/C). This parameter change reduces thermal mismatch stress on the low-k layers during temperature cycling while maintaining the reliability benefits of low-k interconnect materials.
Solution Approach 2:
The patent uses a composite underfill material comprising a polymer matrix combined with filler particles (such as silica, alumina, or boron nitride) specifically selected to achieve a CTE of approximately 8 ppm/C. This composite structure allows tailoring of thermal expansion properties to match the low-k dielectric layer while providing mechanical support and stress distribution.
2Reliability
If lead-free solder bumps are used, then environmental compliance is improved, but solder bumps become brittle and crack during temperature cycling
Solution Approach 1:
The patent changes the CTE parameter of the underfill material to approximately 8 ppm/C, which matches the low-k dielectric layer and reduces differential thermal expansion. This reduces the strain amplitude experienced by lead-free solder bumps during temperature cycling, preventing fatigue cracking while maintaining environmental compliance.
Solution Approach 2:
The underfill material acts as an intermediary between the substrate and the lead-free solder bumps, absorbing and distributing thermal stresses. By having an CTE matched to the low-k layer, the underfill serves as a stress buffer that protects the brittle lead-free solder joints from thermal-induced cracking.
3Reliability
If conventional underfill materials with high CTE (30-50 ppm/C) are used, then solder ball stress is reduced, but low-k dielectric layers experience high stress and underfill delamination occurs
Solution Approach 1:
The patent fundamentally changes the CTE parameter of the underfill material from conventional high values (30-50 ppm/C) to a low value of approximately 8 ppm/C, matching the low-k dielectric layer. This parameter change eliminates the CTE mismatch between underfill and low-k layer, preventing delamination while still providing stress relief for solder balls through the stratified structure.
Solution Approach 2:
The patent implements a stratified underfill structure with different layers having different CTE values. The first layer adjacent to the substrate has higher CTE to protect solder balls, while the second layer adjacent to the die has CTE matched to the low-k dielectric (8 ppm/C) to prevent delamination. This local differentiation of material properties resolves the conflicting requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The stratified underfill layer effectively reduces thermal-induced stress on solder bumps, enhancing the reliability and fatigue life of flip chip packages by matching the CTE of the die and substrate, thereby preventing cracking and delamination.
Implementation Method 1
The die and the package substrate or PCB typically have very different coefficients of thermal expansion (CTE) from each other. The underfill absorbs some of the residual stresses, to reduce the stress within the solder balls, and in the interfaces between the solder balls and the die.
Implementation Method 2
The mixture is dispensed to substantially fill a gap between the die and the package substrate or printed circuit board. The filler material is allowed to at least partially settle after the dispensing step.
Data Source
AI summary
A method includes joining an integrated circuit die having at least one low-k dielectric layer to a package substrate or printed circuit board using a plurality of solder bumps located between the die and the package substrate or printed circuit board. The low-k dielectric layer has a dielectric constant of about 3.0 or less. The solder bumps have a lead concentration of about 5% or less. A stratified underfill is formed between the die and the package substrate or printed circuit board.