Stratified Underfill for Semiconductor Chip Thermal Stress
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Solution Overview
Problem
Conventional semiconductor chip underfills with uniform bulk modulus and coefficient of thermal expansion (CTE) fail to adequately compensate for the disparate CTE between the chip and the package substrate, leading to stress on solder bumps and potential delamination.
Innovation Solution
A stratified underfill layer with varying bulk modulus is formed by concentrating larger and smaller filler particles near the substrate and chip respectively, or varying density particles, to create a gradient in bulk modulus that matches the CTE of the chip and substrate, reducing thermal stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional uniform underfill material is used, then manufacturing is simple, but thermal stress compensation is inadequate due to abrupt CTE differences
Solution Approach 1:
The underfill material is designed with spatially varying properties: larger filler particles concentrated near the substrate provide higher bulk modulus where needed for stress compensation, while smaller particles near the chip maintain appropriate compliance. This local differentiation of material composition enables targeted thermal stress management without requiring a completely complex multi-layer structure.
Solution Approach 2:
The underfill employs a composite material system combining epoxy resin with bimodal filler particles (silica and/or alumina) of different sizes and densities. This composite approach allows the material to exhibit both the flow characteristics needed for application and the mechanical properties needed for stress compensation, resolving the contradiction between simplicity and performance.
2Strength
If larger filler particles are used throughout the underfill, then bulk modulus increases, but stress on solder bumps increases due to excessive rigidity near the chip
Solution Approach 1:
The patent applies local quality by concentrating larger filler particles (higher bulk modulus contribution) specifically in the region proximate to the substrate where high strength is needed for CTE compensation, while using smaller particles near the chip where excessive rigidity would harm solder bumps. This spatial differentiation resolves the contradiction between needing high bulk modulus and avoiding excessive stress.
3Reliability
If uniform filler particle size is used, then manufacturing is easier, but CTE matching between chip and substrate is insufficient
Solution Approach 1:
The patent changes the particle size parameter within the underfill material to achieve graded CTE properties. By incorporating a bimodal distribution of filler particle sizes with different densities, the material achieves continuous CTE transition from chip to substrate, improving thermal compatibility without requiring multiple discrete processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The stratified underfill layer effectively reduces thermal stress on solder bumps by increasing bulk modulus near the substrate and maintaining a lower bulk modulus near the chip, preventing delamination and improving reliability.
Implementation Method 1
a first plurality of filler particles that have a first average density and a second plurality of filler particles that have a second average density lower than the first average density such that the first plurality of filler particles is concentrated proximate the substrate and the second plurality of filler particles is concentrated proximate the semiconductor chip
Implementation Method 2
Surface tension forces tend to draw the deposited underfill material into the voids between the semiconductor chip and the substrate
Data Source
AI summary
Various semiconductor chip underfills and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes coupling a semiconductor chip to a substrate to leave a gap therebetween, and forming an underfill layer in the gap. The underfill layer includes a first plurality of filler particles that have a first average size and a second plurality of filler particles that have a second average size smaller than the first average size such that the first plurality of filler particles is concentrated proximate the substrate and the second plurality of filler particles is concentrated proximate the semiconductor chip so that a bulk modulus of the underfill layer is larger proximate the substrate than proximate the semiconductor chip.