Two-Stage Stream Cipher PRNG for High Linear Complexity
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Solution Overview
Problem
Existing pseudorandom number generators with linear feedback shift registers have limited linear complexity and period length, making them unsuitable for cryptographic applications due to ease of prediction and vulnerability to cryptographic attacks, while increasing the number of memory cells to enhance these features leads to increased hardware costs and vulnerability to localization by attackers.
Innovation Solution
A pseudorandom number generator using a two-stage combining process with elemental shift registers having non-linear feedback, where 2n sequences are combined in an intermediate processing stage and then with a subgroup of k sequences in a final processing stage to produce an output sequence, maximizing correlation immunity and linear complexity while minimizing hardware requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of memory cells in the shift register is increased to enhance period length and linear complexity, then the cryptographic security is improved, but the hardware costs and chip area increase
Solution Approach 1:
The invention divides the pseudorandom number generator into multiple independent elemental shift registers (first shift register, second shift register, etc.) that operate in parallel. Each elemental shift register has a relatively small number of memory cells, but their combined output sequences are mixed through combining means to achieve high linear complexity and cryptographic security without requiring a single large shift register, thus reducing overall chip area.
2Reliability
If the number of memory cells is increased to improve linear complexity, then the resistance to cryptographic attacks is enhanced, but the hardware costs increase
Solution Approach 1:
The system uses multiple elemental shift registers with fewer memory cells each, combined with combining means that mix their outputs. This segmentation approach achieves high linear complexity (resistance to cryptographic attacks) while keeping individual register sizes small, thereby reducing overall hardware complexity and costs compared to a single large shift register.
Solution Approach 2:
The combining means merges the output sequences from multiple elemental shift registers through mathematical operations (such as multiplication and addition in finite fields). This merging process increases the linear complexity of the final output sequence, enhancing resistance to cryptographic attacks while using efficient circuit operations that minimize hardware resource requirements.
3Reliability
If more memory cells are used to extend the period length, then the output sequence becomes less predictable, but the chip area occupied increases
Solution Approach 1:
The invention uses multiple elemental shift registers whose output sequences are combined through mathematical operations. The period length of the final output sequence becomes a function of the periods of individual registers and the combining operations, achieving extended effective period and reduced predictability without proportionally increasing chip area, as the combining means use efficient circuit implementations.
Data Source
AI summary
A pseudorandom number generator includes a unit for providing a number of 2n sequences of numbers, n being greater than or equal to 2. The sequences of numbers are combined by a unit such that at first all the sequences of numbers are combined with one another in an intermediate processing stage to obtain an intermediate processing sequence, and that subsequently a subgroup of k sequences of numbers is combined with the intermediate processing sequence in a final processing stage to obtain the output sequence.