Stream Clock Recovery Using PLL Feedback and Small FIFO Buffers
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Solution Overview
Problem
Conventional systems for regenerating stream clock signals in data streams, such as in DisplayPort, require complex hardware and large buffer storage due to unrelated link and stream clock signals, leading to inaccuracies and display artifacts.
Innovation Solution
A method and apparatus that adjust the stream clock signal based on measurements of clock pulses and buffer storage levels, using a low-resolution phase locked loop and a small FIFO buffer, to maintain synchronization and reduce hardware complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional systems use significant hardware and large buffer storage to regenerate stream clock signals, then clock signal regeneration can be achieved, but hardware complexity and buffer size increase
Solution Approach 1:
The patent changes the operational parameters of the phase-locked loop by using fractional division ratios to generate the stream clock frequency from the link clock. This allows accurate clock regeneration without requiring complex hardware, as the frequency relationship is established through programmable divider ratios rather than complex synthesis circuits
Solution Approach 2:
The patent extracts only the essential timing information (timestamps) from the data stream to regenerate the stream clock, rather than using significant hardware to process the entire data stream. This extraction approach maintains regeneration accuracy while reducing hardware complexity
2Stability of the object's composition
If conventional systems use large buffer storage to store recovered stream data, then data synchronization can be maintained, but buffer storage requirements increase
Solution Approach 1:
The patent uses a feedback mechanism where the system continuously monitors the relationship between link clock and stream clock frequencies, and dynamically adjusts the phase-locked loop operation to maintain synchronization. This feedback control maintains stable data synchronization with minimal buffer storage, as buffers are only sized to handle small timing variations rather than large drift compensations
3Adaptability or versatility
If link clock and stream clock signals are allowed to drift with respect to each other, then clock independence is maintained, but synchronization accuracy deteriorates
Solution Approach 1:
The patent implements a dynamic synchronization system where the phase-locked loop continuously adjusts the stream clock frequency based on the detected relationship with the link clock. This dynamic adjustment maintains synchronization accuracy despite clock independence, as the system adapts to frequency variations in real-time rather than requiring fixed frequency relationships
Solution Approach 2:
The patent performs preliminary measurement of the frequency relationship between link and stream clocks using timestamps, and uses this pre-acquired information to configure the phase-locked loop for accurate regeneration. This preliminary action enables the system to maintain synchronization accuracy while preserving clock independence
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for accurate regeneration of stream clock signals with reduced hardware complexity and buffer size, minimizing display artifacts and compliance violations.
Implementation Method 1
using a low-resolution phase locked loop and a small FIFO buffer, to maintain synchronization
Data Source
AI summary
Embodiments of the invention are generally directed to adjustment of clock signals regenerated from a data stream. An embodiment of a method includes receiving a data stream from a transmitting device via a communication link, the data stream including stream data, a link clock signal, and timestamps to indicate a relationship between the link clock signal and a stream clock signal. The method further includes adjusting the stream clock based at least in part on one or more measurements related to the data stream, the one or more measurements including a count of a number of pulses of the stream clock during a period of time, or a measurement of a number of data elements from the data stream stored in a buffer at a certain point in time.