Stream Decompression Circuit Using Coded-Length FIFO Control
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Solution Overview
Problem
Conventional hardware implementations of stream decoders for VESA display stream compression (DSC) require complex and costly circuit structures to manage the output order of sub-streams Y/Co/Cg, which hinders product competitiveness.
Innovation Solution
A stream decompression circuit comprising a coding length FIFO and a calculation circuit that controls a multiplexer to output sub-streams based on coded lengths, eliminating the need for a stream decoder and simplifying the circuit architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a stream decoder is implemented in hardware to control the multiplexer output order, then the sub-streams can be output in the correct order, but the circuit structure becomes complicated and hardware cost increases significantly
Solution Approach 1:
The patent extracts the essential function of the stream decoder (tracking coded lengths and determining output order) and separates it from the complex decoder hardware. Instead of using a full stream decoder, the invention uses a simplified approach with a coded length register that stores only the necessary length information, eliminating the need for VLD, lookup tables, and other complex components while maintaining correct sub-stream output ordering.
Solution Approach 2:
The patent uses a coded length register that stores copies of the coded length information from the VLC circuit. This simple register acts as a lightweight alternative to the complex stream decoder, capturing only the essential timing and ordering information needed to control the multiplexer without requiring the full decoding functionality.
2Productivity
If a stream decoder is implemented in hardware to manage sub-stream output, then the decompression can be performed, but the hardware design cost increases significantly
Solution Approach 1:
The patent replaces the expensive, complex stream decoder hardware with a simple coded length register and basic control logic. This lightweight solution performs the essential function of tracking sub-stream lengths and controlling output order without the high hardware design cost of a full stream decoder implementation.
3Ease of operation
If conventional multiplexer control is used with a stream decoder, then sub-streams can be output according to bits consumed, but the circuit architecture becomes large and complex
Solution Approach 1:
The patent segments the functionality into distinct simple components: the VLC circuit for compression, the coded length register for storing length information, and the multiplexer for output control. This segmentation eliminates the need for a monolithic complex stream decoder while maintaining the ability to control multiplexer output based on coded lengths.
Data Source
AI summary
A stream decompression circuit is disclosed. The stream decompression circuit includes a coding length first-in-first-out (FIFO) and a calculation circuit. The coding length FIFO is coupled to a variable length coding (VLC) circuit and used to store a coding length that the VLC circuit codes sub-streams and output a specific number of bits when the coding length accumulates over the specific number of bits. The calculation circuit is coupled between the coding length FIFO and a multiplexer circuit and used to calculate a number of bits required for decompression and output an output multiplex control signal to the multiplexer circuit to control the multiplexer circuit to output the sub-streams according to a specific order.