Stream FIFO Insertion in Heterogeneous Multi-Core Compilation
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Solution Overview
Problem
Existing compilers for multi-core architectures do not effectively address heterogeneous architectures, particularly in mapping compute kernels to processor cores and data structures to memory banks, and routing stream data and DMA data between processor cores and programmable logic.
Innovation Solution
A compilation flow for a heterogeneous multi-core architecture that involves obtaining a graph representation of an application, mapping kernels onto data processing engines (DPEs) and data structures onto memory, routing communication channels, and adding FIFO buffers to communication channels to generate implementation data for programming a System-on-Chip (SoC).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If existing compilers are used for multi-core architectures, then compilation can be performed, but they cannot effectively address heterogeneous architectures including mapping kernels to processor cores and routing stream data between cores and programmable logic
Solution Approach 1:
The compilation process is divided into distinct stages: graph representation parsing, kernel mapping to DPEs, data structure mapping to memory banks, communication channel routing, and FIFO insertion. Each stage handles a specific aspect of heterogeneous architecture compilation, enabling the compiler to effectively process complex multi-core applications while maintaining adaptability to the target architecture.
2Productivity
If FIFO buffers are added to communication channels, then data flow synchronization and performance are improved, but device complexity increases
Solution Approach 1:
The compiler performs preliminary analysis of the application graph to identify communication channels that require FIFO buffers before code generation. By determining FIFO requirements during the compilation phase rather than at runtime, the system optimizes execution performance while managing complexity through static analysis and automated buffer placement in the communication path between DPEs.
3Productivity
If kernel mapping and data structure allocation are optimized, then execution efficiency improves, but compilation complexity increases
Solution Approach 1:
The patent introduces an intermediate representation (graph representation) that models the application's computational kernels and data dependencies. This graph serves as a mediator between the high-level application code and the low-level heterogeneous architecture, enabling the compiler to perform optimized mapping of kernels to DPEs and data structures to memory banks while managing compilation complexity through structured analysis.
Data Source
AI summary
An example method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array includes obtaining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels, mapping, based on the graph, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array, routing communication channels between DPEs and circuitry of the application configured in programmable logic of the SOC, adding at least one first-in-first-out (FIFO) buffer to at least one of the communication channels, and generating implementation data for programming the SOC to implement the application based on results of the mapping and the routing.